Papers

WCAE21: Digital Design and RISC-V Computer Architecture Textbook: paper, slides, Lightning slides
ICIT20: ARM-based Digital Design and Computer Architecture Curriculum
PhysReviewE2018: Microchaos in Human Postural Balance: Sensory Dead Zones and Sampled Time-Delayed Feedback
MSE17: Design flows and collateral for the ASAP 7nm FinFET predictive process design kit
IET17: MIPSfpga: Using a commercial MIPS soft-core in computer architecture education
TNucSci15: Bias Dependence of Single-Event Upsets in 16 nm FinFET D Flip-Flops
TVLSI15: Sequential Element Timing Parameter Definition Considering Clock Uncertainty
TVLSI14: A Compact Transregional Model for Digital MOS Circuits Operating Near Threshold
Asilomar13: Comparison of Parallelized Radix-2 and Radix-4 Scalable Montgomery Multipliers
Asilomar13: Implementation of 64-bit Jackson Adders
MSE13: Introductory Digital Design & Computer Architecture Curriculum
JSSC13: Bubble Razor
Asilomar12: Yield-Driven Minimum Energy CMOS Cell Design
ISSCC12: Bubble Razor
Asilomar11: Implementation of 32-bit Ling and Jackson Adders
ICM10: A Transregional Model for Near-Threshold Circuits with Application to Minimum-Energy Operation
MWSCAS10: Long-Tail Behavior of Process Variation with Application to Domino Keeper Sizing
Asilomar08: Parallelized Booth-Encoded Radix-8 Montgomery Multipliers
VLSISOC08: Parallelized Booth-Encoded Radix-4 Montgomery Multipliers
ICCD08: Energy-Delay Tradeoffs in 32-bit Static Shifters
JICS08: Parallelized Radix-4 Scalable Montgomery Multipliers
SPIE08: An Approach to Instrument Qualified Visual Range
DAC/ISSCC08: A MIPS R2000 Implementation
SBCCI07: Parallelized Radix-4 Scalable Montgomery Multipliers
VLSISoC07: Parallelized Radix-2 Scalable Montgomery Multiplier
Backpacker Magazine April 07: Strawberry Valley Loop
Asilomar06: Quotient Pipelined Very High Radix Scalable Montgomery Multipliers
RCE06: From Zero to One: An Introduction to Digital Design and Computer Architecture
Aerospace06: Adaptive Two-Channel Automatic Gain Control System
Asilomar05: Parallelized Very High Radix Scalable Montgomery Multipliers
ICCD05: Surfliner: A Distortionless Electrical Signaling Scheme for Speed of Light On-Chip Communications
IWSOC05: Very High Radix Scalable Montgomery Multipliers
Arith05: An Improved Unified Scalable Radix-2 Montgomery Multiplier
MSE05: Inexpensive Student-Assembled FPGA / Microcontroller Board
Asilomar04: Logical Effort of Higher Valency Adders
SPI04: Bounding Bus Delay and Noise Effects of On-Chip Inductance
TCOMP04: An Exponentiation Unit for an OpenGL Lighting Engine
Asilomar03: Logical Effort of Carry Propagate Adders
Asilomar03: A Taxonomy of Parallel Prefix Networks
ASEE03: A Cross-Cultural VLSI Design Project (talk)
MSE03: TestosterICs: A Low-Cost Functional Chip Tester
GLSVLSI03: Comparison of Noise Tolerant Precharge (NTP) to Conventional Feedback Keepers for Dynamic Logic
FIE02: The Microprocessor as a Microcosm: A Hands-On Approach to VLSI Design Education (talk)
TVLSI: Statistical Clock Skew Modeling with Data Delay Variations
ASEE 02: A Freshman Advising Seminar on Digital Electronics and Chip Design
Asilomar 01: A Powering Unit for an OpenGL Lighting Engine
TCAD99: Timing Analysis with Clock Skew
Async99: A Counterflow Pipeline Experiment
Skew-Tolerant Circuit Design (Stanford Ph.D. Thesis)
Tau 99: Timing Analysis with Clock Skew
ARITH13: SRT Division Architectures and Implementations
JSSC: Skew-tolerant Domino Circuits
ISSCC97: Skew-tolerant Domino Circuits

Talks