E158: Introduction to CMOS VLSI Design


Administrative
Syllabus
Schedule 		Textbook Links
Computer Organization and Design
Logical Effort
Skew-Tolerant Circuit Design
Corrections to Weste & Eshraghian 		Handouts
Structural Design with Verilog
Labs
Lab 1
Lab 2
Lab 3
Lab 4
Lab 5
Final Project
Final Project Grading Sheet 		Problem Sets
PS 1
PS 2
PS 3
PS 4
PS 5
PS 6 		Projects
Spring 2001 Projects
Lectures
1: Introduction
2: Fabrication & Layout
3: Transistors & Gates
4: Gates, Cap, and Sim
5: Logic
6: Hardware Desc. Lang.
7: Synthesis and Floorplanning
8: Clocking
9: Cell Design
10: Circuit Families
11: Memory Design
12: Delay Estimation & Sizing
13: Logical Effort 1
14: Logical Effort 2
15: Adders
16: Datapath Functional Units
17: Economics & Scaling
18: Design for Testability
19: IO
20: Low Power
21: Skew-Tolerant Static Ckts
22: Skew-Tolerant Domino Ckts
23: Trends in VLSI 		Tools
Electric
MOSIS IC Fabrication
MOSIS SCMOS Design Rules
Gemini User Manual
Gemini Tips
IRSIM Tutorial
IRSIM User Manual (pdf)
Spice Manual
VLSI Links