Note: in the figure above, as the assumed polarities of both and
are the opposite to those assumed in plot (b) below, the negative
signs for both
and
in the plot should be dropped.
Solution:
,
,
, or
.
If and
,
can be estimated from
figure (b), and correspondingly,
and
. When
,
,
, and
.
Solution:
Solution: The load line goes through the points
and
.
Its intersection with the curve
is approximately at
, where we can also find
and
.
Note: As the convention in the schematics of transistor circuits,
the bottom horizontal line is treated as the ground, and all voltages,
such as ,
and
are measured with respect to the
ground as the reference point.
Hint: The relationship is only valid in the
linear region in the middle range of the load line. However, in
the cut-off region (close to the horizontal axis) and the saturation
region (close to the vertical axis), the above relationship no
longer holds and the actual output current
and
can
only be found graphically in the output characteristic plot.
Solution:
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Solution: When ,
is cut-off. When
,
,
is saturated with
and
(instead of
).
The same is true for
. From the table below we see that the
circuit is a NOR (not OR) gate (high voltage for True and low
voltage for False).
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