The LXRE Processor

For this class, you'll be designing a processor that implements the LXRE (pronounced Luxury) instruction set. This instruction set is based on the DLX Processor, which in turn is based on MIPS. The instruction set was chosen to be on the simpler end of processors, while still being very similar to actual instruction sets.

Overview

The LXRE processor uses a RISC architecture very similar to the MIPS processor that you have discussed in E85. As with MIPS, all instructions are 32 bits long, and to load a 32 bit immediate requires two instructions. The LXRE processor also has 32 32-bit registers, as in MIPS register 0 is always 0, and register 31 is the fixed destination for jump and link instructions. In addition to the register file, the LXRE processor also has a 32 bit program counter.

Instruction Set

Instruction Formats

In the LXRE machine code there are three different instruction types, R-type, I-type, and J-type. All formats specify a type followed by an opcode, but the information in the remainder of the format varies by format. R-type (register) instructions specify three registers in the instruction - the destination register followed by two source registers. I-type (immediate) instructions specify one destination register, on source register, and a 16-bit immediate value. J-type (jump) instructions specify a single 26 bit signed value.

Instructions

The following table lists the instructions that your implementation of LXRE must support. The operations for each opcode are specfied using C syntax and operators. The prefix (unsigned) before immediate values indicates that the immediate 0-padded, otherwise it is sign extended.

External Memory

The LXRE Processor uses a simple memory interface and uses memory mapped IO for input and output. The memory system has two read ports and one write port. For each port there is an address bus, data bus, valid cpu and valid mem signals.

Writing

• Wait until valid mem is low.
• Load the address and the data onto the busses.
• Raise valid cpu.
• Wait until valid mem is raised.
• Lower valid cpu.

Reading

• Load the address bus.
• Wait until valid mem is low.
• Raise valid cpu.
• Wait until valid mem is raised.
• Get data off bus.
• Lower valid cpu.

Segmentation and Memory Mapped IO

The memory is segmented in the C-simulator for debugging purposes, additionally some memory locations are reserved for memory IO.

• 0x00000000 - 0x00000FFF : Protected memory, cannot read, write, or execute any address in this segmented.
• 0x00001000 - 0x00001FFF : Input/Output, memory locations listed below have special side effects, other locations are protected.
  • 0x00001000 : TERM, writing or reading this location writes or reads to the terminal.
  • 0x00001010 : HALT, writing to this location halts the program.
  • 0x00001100 - 0x000012FF : PROF LXRE Profiler.
  • 0x00001800 - 0x00001FFF : LSC LXRE SIMD Coprocessor.
• 0x00002000 - 0x000007FFF : Read-Only, can only read from this segment.
• 0x00008000 - 0x008000000 : Code, can only execute this segement.
• 0x00800000 - 0xFFFFFFFFF : Heap - Stack - Globals, allows general read/write access.