References

A majority of references are from IEEE publications and can be obtained from ieeexplore.ieee.org. An electronic version of this bibliography with hyperlinks is available at www.cmosvlsi.com. The IEEE Journal of Solid-State Circuits is cited heavily and is abbreviated as JSSC.

[Abdollahi04] A. Abdollahi, F. Fallah, and M. Pedram, "Leakage current reduction in CMOS VLSI circuits by input vector control," IEEE Trans. VLSI, vol. 12, no. 2, Feb. 2004, pp. 140-154.

[Acken83] J. Acken, "Testing for bridging faults (shorts) in CMOS circuits," Proc. Design Automation Conf., 1983, pp. 717-718.

[Afghahi90] M. Afghahi and C. Svensson, "A unified single-phase clocking scheme for VLSI systems," JSSC, vol. 25, no. 1, Feb. 1990, pp. 225-233.

[Agans06] D. Agans, Debugging, New York: Amacon, 2006.

[Agarwal01] V. Agarwal, S. Keckler, and D. Burger, "The effect of technology scaling on microarchitectural structures," Computer Architecture and Technology Laboratory Technical Report TR2000-02, University of Texas at Austin, 2001.

[Agarwal04] A. Agarwal, V. Zolotov, and D. Blaauw, "Statistical clock skew analysis considering intra-die process variations," IEEE Trans. CAD, vol. 23, no. 8, Aug. 2004, pp. 1231-1242.

[Agarwal07] A. Agarwal, K. Kang, S. Bhunia, J. Gallagher, and K. Roy, "Device-aware yield-centric dual-V_t design under parameter variations in nanoscale technologies," IEEE Trans. VLSI, vol. 15, no. 6, Jun. 2007, pp. 660-671.

[Agarwal07b] K. Agarwal, R. Rao, D. Sylvester, and R. Brown, "Parametric yield analysis and optimization in leakage dominated technologies," IEEE Trans. VLSI, vol. 15, no. 6, Jun. 2007, pp. 613-623.

[Agrawal08] B. Agrawal and T. Sherwood, "Ternary CAM power and delay model: extensions and uses," IEEE Trans. VLSI, vol. 16, no. 5, May 2008, pp. 554-564.

[Aisaka02] K. Aisaka et al., "Design rule for frequency-voltage cooperative power control and its application to an MPEG-4 decoder," Proc. VLSI Circuits Symp., 2002, pp. 216-217.

[Alexander75] J. Alexander, "Clock recovery from random binary signals," Electronics Letters, vol. 11, no. 22, Oct. 30, 1975, pp. 541-542.

[Allam00] M. Allam, M. Anis, and M. Elmasry, "High-speed dynamic logic styles for scaled-down CMOS and MTCMOS technologies," Proc. Intl. Symp. Low Power Electronics and Design, 2000, pp. 155-160.

[Alon05] E. Alon, V. Stojanovic, and M. Horowitz, "Circuits and techniques for high-resolution measurement of on-chip power supply noise," JSSC, vol. 40, no. 4, Apr. 2005, pp. 820-828.

[Alvandpour02] A. Alvandpour, R. Krishnamurthy, K. Soumyanath, and S. Borkar, "A sub-130-nm conditional keeper technique," JSSC, vol. 37, no. 5, May 2002, pp. 633-638.

[Amrutur98] B. Amrutur and M. Horowitz, "A replica technique for wordline and sense control in low-power SRAM's," JSSC, vol. 33, no. 8, Aug. 1998, pp. 1208-1219.

[Amrutur00] B. Amrutur and M. Horowitz, "Speed and power scaling of SRAM's," JSSC, vol. 35, no. 2, Feb. 2000, pp. 175-185.

[Amrutur01] B. Amrutur and M. Horowitz, "Fast low-power decoders for RAMs," JSSC, vol. 36, no. 10, Oct. 2001, pp. 1506-1515.

[Anastasakis02] D. Anastasakis, R. Damiano, H. Ma, and T. Stanion, "A practical and efficient method for compare-point matching," Proc. Design Automation Conf., Jun. 2002, pp. 305-310.

[Anderson02] F. Anderson, J. Wells, and E. Berta, "The core clock system on the next generation Itanium microprocessor," Proc. IEEE Intl. Solid-State Circuits Conf., Feb. 2002, pp. 146-147, 453.

[Ando80] H. Ando, "Testing VLSI with random access scan," Digest of Papers COMPCON 80, Feb. 1980, pp. 50-52.

[Anis03] M. Anis and M. Elmasry, Multi-Threshold CMOS Digital Circuits, Norwell, MA: Kluwer, 2003.

[Arnaud08] F. Arnaud et al., "32 nm general purpose bulk CMOS technology for high performance applications at low voltage," Proc. Intl. Electron Devices Meeting, Dec. 2008, pp. 1-4.

[Artisan02] Artisan Components, TSMC 0.18 mm Process 1.8-Volt SAGE-X Standard Cell Library Databook, Release 4.0, Feb. 2002.

[Asenov07] A. Asenov, "Simulation of statistical variability in nano MOSFETs," Proc. VLSI Technology Symp., Jun. 2007, pp. 86-87.

[Auth08] C. Auth et al., "45 nm high-k+ metal gate strain-enhanced transistors," Intel Technology Journal, vol. 12, no. 2, Jun. 2008, pp. 77-85.

[Baghini02] M. Baghini and M. Desai, "Impact of technology scaling on metastability performance of CMOS synchronizing latches," Proc. Intl. Conf. VLSI Design, 2002, pp. 317-322.

[Bai04] P. Bai et al., "A 65 nm logic technology featuring 35 nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, low-k ILD and 0.57 mm² SRAM cell," Proc. Intl. Electron Devices Meeting, Dec. 2004, pp. 657-660.

[Bailey98] D. Bailey and B. Benschneider, "Clocking design and analysis for a 600-MHz Alpha microprocessor," JSSC, vol. 33, no. 11, Nov. 1998, pp. 1627-1633.

[Baker97] K. Baker and J. van Beers, "Shmoo plotting: the black art of IC testing," IEEE Design and Test of Computers, vol. 14, no. 3, Jul.-Sep. 1997, pp. 90-97.

[Bakoglu90] H. Bakoglu, Circuits, Interconnections, and Packaging for VLSI, Reading, MA: Addison-Wesley, 1990.

[Barke88] E. Barke, "Line-to-ground capacitance calculation for VLSI: a comparison," IEEE Trans. Computer-Aided Design, vol. 7, no. 2, Feb. 1988, pp. 295-298.

[Barry03] J. Barry, E. Lee, and D. Messerschmitt, Digital Communication, 3rd ed., New York: Springer, 2003.

[Barth08] J. Barth et al., "A 500 MHz random cycle, 1.5 ns latency, SOI embedded DRAM macro featuring a three-transistor micro sense amplifier," JSSC, vol. 43, no. 1, Jan. 2008, pp. 86-95.

[Baugh73] C. Baugh and B. Wooley, "A two's complement parallel array multiplication algorithm," IEEE Trans. Computers, vol. C-22, no. 12, Dec. 1973, pp. 1045-1047.

[Baumann01] R. Baumann, "Soft errors in advanced semiconductor devices-part I: the three radiation sources," IEEE Trans. Device & Materials Reliability, vol. 1, no. 1, Mar. 2001, pp. 17-22.

[Baumann05] R. Baumann, "Soft errors in advanced computer systems," IEEE Design & Test of Computers, vol. 22, no. 3, May-Jun. 2005, pp. 258-266.

[Beaumont-Smith99] A. Beaumont-Smith, N. Burgess, S. Lefrere, and C. Lim, "Reduced latency IEEE floating-point adder architectures," Proc. IEEE Symp. Computer Arithmetic, Apr. 1999, pp. 35-42.

[Beaumont-Smith01] A. Beaumont-Smith and C. Lim, "Parallel prefix adder design," Proc. IEEE Symp. Computer Arithmetic, 2001, pp. 218-225.

[Bedrij62] O. Bedrij, "Carry-select adder," IRE Trans. Electronic Computers, vol. 11, Jun. 1962, pp. 340-346.

[Belluomini05] W. Belluomini et al., "An 8GHz floating-point multiply," Proc. Intl. Solid-State Circuits Conf., Feb. 2005, pp. 374-375, 604.

[Bergeron05] J. Bergeron, E. Cerny, A. Hunter, and A. Nightingale, Verification Methodology Manual for SystemVerilog, New York: Springer, 2005.

[Bernstein99] K. Bernstein, K. Carrig, C. Durham, P. Hansen, D. Hogenmiller, E. Nowak, and N. Roher, High Speed CMOS Design Styles, Boston: Kluwer Academic Publishers, 1999.

[Bernstein00] K. Bernstein and N. Rohrer, SOI Circuit Design Concepts, Boston: Kluwer Academic Publishers, 2000.

[Bernstein06] K. Bernstein et al., "High-performance CMOS variability in the 65-nm regime and beyond," IBM J. Research and Dev., vol. 50, no. 4/5, Jul./Sep. 2006, pp. 433-449.

[Bewick94] G. Bewick, "Fast Multiplication: Algorithms and Implementation," Ph.D. thesis, Stanford University, CSL-TR-94-617, 1994.

[Bhavnagarwala01] A. Bhavnagarwala, Xinghai Tang, and J. Meindl, "The impact of intrinsic device fluctuations on CMOS SRAM cell stability," JSSC, vol. 36, no. 4, Apr. 2001, pp. 658-665.

[Bhavnagarwala04] A. Bhavnagarwala et al., "A transregional CMOS SRAM with single, logic V_DD and dynamic power rails," Proc. VLSI Circuits Symp., Jun. 2004, pp. 292-293.

[Bhavnagarwala05] A. Bhavnagarwala et al., "Fluctuation limits & scaling opportunities for CMOS SRAM cells," Proc. Intl. Electron Devices Meeting, Dec. 2005, pp. 659-662.

[Black69] J. Black, "Electromigration-A brief survey and some recent results," IEEE Trans. Electron Devices, vol. ED-16, no. 4, Apr. 1969, pp. 338-347.

[Blackburn96] J. Blackburn, L. Arndt, and E. Swartzlander, "Optimization of spanning tree carry lookahead adders," Proc. 30th Asilomar Conf. Signals, Systems, and Computers, vol. 1, 1996, pp. 177-181.

[Bohr95] M. Bohr, "Interconnect scaling-the real limiter to high performance ULSI," Proc. Intl. Electron Devices Meeting, Dec. 1995, pp. 241-244.

[Bohr96] M. Bohr et al., "A high performance 0.25 mm logic technology optimized for 1.8 V operation," Proc. Intl. Electron Devices Meeting, Dec. 1996, pp. 847-850.

[Booth51] A. Booth, "A signed binary multiplication technique," Quarterly J. Mechanics and Applied Mathematics, vol. IV, pt. 2, Jun. 1951, pp. 236-240.

[Bowhill95] W. Bowhill et al., "Circuit implementation of a 300-MHz 64-bit second-generation CMOS Alpha CPU," Digital Technical Journal, vol. 7, no. 1, 1995, pp. 100-115.

[Bowman02] K. Bowman, S. Duvall, and J. Meindl, "Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration," JSSC, vol. 37, no. 2, Feb. 2002, pp. 183-190.

[Bowman09] K. Bowman et al., "Energy-efficient and metastability-immune resilient circuits for dynamic variation tolerance," JSSC, vol. 44, no. 1, Jan. 2009, pp. 49-63.

[Brederlow06] R. Brederlow, R. Prakash, C. Paulus, and R. Thewes, "A low-power true random number generator using random telegraph noise of single oxide-traps," Proc. Intl. Solid-State Circuits Conf., Feb. 2006, pp. 1666-1675.

[Brent82] R. Brent and H. Kung, "A regular layout for parallel adders," IEEE Trans. Computers, vol. C-31, no. 3, Mar. 1982, pp. 260-264.

[Brewer08] J. Brewer and M. Gill, eds., Nonvolatile Memory Technology with Emphasis on Flash, Piscataway, NJ: IEEE Press, 2008.

[Brooks95] F. Brooks, The Mythical Man-Month, Boston: Addison-Wesley, 1995.

[Brown03] A. Brown, "Fast films," IEEE Spectrum, vol. 40, no. 2, Feb. 2003, pp. 36-40.

[Brunvand09] E. Brunvand, Digital VLSI Chip Design with Cadence and Synopsys CAD Tools, Boston: Addison Wesley, 2009.

[Brusamarello08] L. Brusamarello, R. da Silva, G. Wirth, and R. Reis, "Probabilistic approach for yield analysis of dynamic logic circuits," IEEE Trans. Circuits & Systems, vol. 55, no. 8, Sep. 2008, pp. 2238-2248.

[Budnik06] M. Budnik and K. Roy, "A power delivery and decoupling network minimizing ohmic loss and supply voltage variation in silicon nanoscale technologies," IEEE Trans. VLSI, vol. 14, no. 12, Dec. 2006, pp. 1336-1346.

[Burd00] T. Burd, T. Pering, A. Stratakos, and R. Brodersen, "A dynamic voltage scaled microprocessor system," JSSC, vol. 35, no. 11, Nov. 2000, pp. 1571-1580.

[Burgess02] N. Burgess, "The flagged prefix adder and its applications in integer arithmetic," J. VLSI Signal Processing, 2002, pp. 263-271.

[Burgess09] N. Burgess, "Implementation of recursive Ling adders in CMOS VLSI," Proc. Asilomar Conf. Signals, Systems, and Computers, 2009.

[Burks46] A. Burks, H. Goldstine, and J. von Neumann, Preliminary discussion of the logical design of an electronic computing instrument, part 1, vol. 1, Inst. Advanced Study, Princeton, NJ, 1946.

[Burleson98] W. Burleson, M. Ciesielski, F. Klass, and W. Liu, "Wave-pipelining: a tutorial and research survey," IEEE Trans. VLSI, vol. 6, no. 3, Sep. 1998, pp. 464-474.

[Calhoun04] B. Calhoun, F. Honore, and A. Chandrakasan, "A leakage reduction methodology for distributed MTCMOS," JSSC, vol. 39, no. 5, May 2004, pp. 818-826.

[Calhoun05] B. Calhoun, A. Wang, and A. Chandrakasan, "Modeling and sizing for minimum energy operation in subthreshold circuits," JSSC, vol. 40, no. 9, Sep. 2005, pp. 1778-1786.

[Calhoun06a] B. Calhoun and A. Chandrakasan, "Ultra-dynamic voltage scaling (UDVS) using sub-threshold operation and local voltage dithering," JSSC, vol. 41, no. 1, Jan. 2006, pp. 238-245.

[Calhoun06b] B. Calhoun and A. Chandrakasan, "Static noise margin variation for sub-threshold SRAM in 65-nm CMOS," JSSC, vol. 41, no. 7, Jul. 2006, pp. 1673-1679.

[Calhoun07] B. Calhoun and A. Chandrakasan, "A 256-kb 65-nm sub-threshold SRAM design for ultra-low-voltage operation," JSSC, vol. 42, no. 3, Mar. 2007, pp. 680-688.

[Calin96] T. Calin, M. Nicolaidis, and R. Velazco, "Upset hardened memory design for submicron CMOS technology," IEEE Trans. Nuclear Science, vol. 43, no. 6, Dec. 1996, pp. 2874-2878.

[Calma84] Calma Corporation, GDS II Stream Format, Jul. 1984.

[Carr72] W. Carr and J. Mize, MOS/LSI Design and Application, New York: McGraw-Hill, 1972.

[Celik02] M. Celik, L. Pileggi, and A. Odabasioglu, IC Interconnect Analysis, Boston: Kluwer Academic Publishers, 2002.

[Cenker79] R. Cenker, D. Clemons, W. Huber, J. Petrizzi, F. Procyk, and G. Trout, "A fault-tolerant 64K dynamic random-access memory," IEEE Trans. Electron Devices, vol. 26, no. 6, Jun. 1979, pp. 853-860.

[Chan90] P. Chan and M. Schlag, "Analysis and design of CMOS Manchester adders with variable carry-skip," IEEE Trans. Computers, vol. 39, no. 8, Aug. 1990, pp. 983-992.

[Chan05] S. Chan, K. Shepard, and P. Restle, "Uniform-phase uniform-amplitude resonant-load global clock distributions," JSSC, vol. 40, no. 1, Jan. 2005, pp. 102-109.

[Chan09] S. Chan et al., "A resonant global clock distribution for the cell broadband engine processor," JSSC, vol. 44, no. 1, Jan. 2009, pp. 64-72.

[Chandrakasan92] A. Chandrakasan, S. Sheng, and R. Brodersen, "Low-power CMOS digital design," JSSC, vol. 27, no. 4, Apr. 1992, pp. 473-484.

[Chandrakasan01] A. Chandrakasan, W. Bowhill, and F. Fox, ed., Design of High-Performance Microprocessor Circuits, Piscataway, NJ: IEEE Press, 2001.

[Chaney73] T. Chaney and C. Molnar, "Anomalous behavior of synchronizer and arbiter circuits," IEEE Trans. Computers, vol. C-22, Apr. 1973, pp. 421-422.

[Chaney83] T. Chaney, "Measured flip-flop responses to marginal triggering," IEEE Trans. Computers, vol. C-32, no. 12, Dec. 1983, pp. 1207-1209.

[Chang05] J. Chang et al., "A 130-nm triple-V_t 9-MB third-level on-die cache for the 1.7-GHz Itanium 2 processor," JSSC, vol. 40, no. 1, Jan. 2005, pp. 195-203.

[Chang07] J. Chang et al., "The 65-nm 16-MB shared on-die L3 cache for the dual-core Intel Xeon processor 7100 Series," JSSC, vol. 42, no. 4, Apr. 2007, pp. 846-852.

[Chang08] L. Chang et al., "An 8T-SRAM for variability tolerance and low-voltage operation in high-performance caches," JSSC, vol. 43, no. 4, Apr. 2008, pp. 956-963.

[Chao89] H. Chao and C. Johnston, "Behavior analysis of CMOS D flip-flops," JSSC, vol. 24, no. 5, Oct. 1989, pp. 1454-1458.

[Chappell91] T. Chappell, B. Chappell, S. Schuster, J. Allan, S. Klepner, R. Joshi, and R. Franch, "A 2-ns cycle, 3.8-ns access 512-kb CMOS ECL SRAM with a fully pipelined architecture," JSSC, vol. 26, no. 11, Nov. 1991, pp. 1577-1585.

[Chen96] K. Chen, H. Wann, J. Dunster, P. Ko, C. Hu, and M. Yoshida, "MOSFET carrier mobility model based on gate oxide thickness, threshold and gate voltages," Solid-State Electronics, vol. 39, no. 10, 1996, pp. 1515-1518.

[Chen97] K. Chen, C. Hu, P. Fang, M. Lin, and D. Wollesen, "Predicting CMOS speed with gate oxide and voltage scaling and interconnect loading effects," IEEE Trans. Electron Devices, vol. 44, no. 11, Nov. 1997, pp. 1951-1957.

[Chen03] T. Chen and S. Naffziger, "Comparison of adaptive body bias (ABB) and adaptive supply voltage (ASV) for improving delay and leakage under the presence of process variation," IEEE Trans. VLSI, vol. 11, no. 5, Oct. 2003, pp. 888-899.

[Chen06] J. Chen, L. Clark, and T. Chen, "An ultra-low-power memory with a subthreshold power supply voltage," JSSC, vol. 41, no. 10, Oct. 2006, pp. 2344-2353.

[Chen07] G. Chen, D. Blaauw, T. Mudge, D. Sylvester, and Nam Sung Kim, "Yield-driven near-threshold SRAM design," Proc. Intl. Conf. Computer-Aided Design, Nov. 2007, pp. 660-666.

[Cheng99] Y. Cheng and C. Hu, MOSFET Modeling & BSIM3 User's Guide, Boston: Kluwer Academic Publishers, 1999.

[Cheng00] Y. Cheng, C. Tsai, C. Teng, and S. Kang, Electrothermal Analysis of VLSI Systems, Boston: Kluwer Academic Publishers, 2000.

[Chern92] J. Chern, J. Huang, L. Arledge, P. Li, and P. Yang, "Multilevel metal capacitance models for CAD design synthesis systems," IEEE Electron Device Letters, vol. 13, no. 1, Jan. 1992, pp. 32-34.

[Childs84] R. Childs, J. Crawford, D. House, and R. Noyce, "A processor family for personal computers," Proc. IEEE, vol. 72, no. 3, Mar. 1984, pp. 363-376.

[Chinnery02] D. Chinnery and K. Keutzer, Closing the Gap Between ASIC and Custom: Tools and techniques for high-performance ASIC design, Boston: Kluwer Academic Publishers, 2002.

[Chinnery07] D. Chinnery & K. Keutzer, Closing the Power Gap Between ASIC and Custom, New York: Springer, 2007.

[Choi97] J. Choi, L. Jang, S. Jung, and J. Choi, "Structured design of a 288-tap FIR filter by optimized partial product tree compression," JSSC, vol. 32, no. 3, Mar. 1997, pp. 468-476.

[Chong06] K. Chong, L. McMurchie, and C. Sechen, "A 64b adder using self-calibrating differential output prediction logic," Proc. Intl. Solid-State Circuits Conf., Feb. 2006, pp. 1745-1754.

[Chopra06] K. Chopra, C. Kashyap, H. Su, and D. Blaauw, "Current source driver model synthesis and worst-case alignment for accurate timing and noise analysis," Intl. Workshop on Timing in Synthesis and Specification (TAU), Feb. 2006.

[Choudhury97] M. Choudhury and J. Miller, "A 300 MHz CMOS microprocessor with multi-media technology," Proc. IEEE Intl. Solid-State Circuits Conf., 1997, pp. 170-171.

[Christiansen06] C. Christiansen, J. Gambino, J. Therrien, D. Hunt, and J. Gill, "Effect of wire thickness on electromigration and stress migration lifetime of Cu," Proc. Failure Analysis of Integrated Circuits, Jul. 2006, pp. 349-354.

[Chu86] K. Chu and D. Pulfrey, "Design procedures for differential cascode voltage switch circuits," JSSC, vol. SC-21, no. 6, Dec. 1986, pp. 1082-1087.

[Chu87] K. Chu and D. Pulfrey, "A comparison of CMOS circuit techniques: differential cascode voltage switch logic versus conventional logic," JSSC, vol. SC-22, no. 4, Aug. 1987, pp. 528-532.

[Clark61] C. Clark, "The greatest of a finite set of random variables," Operations Research, vol. 9, no. 2, Mar.-Apr. 1961, pp. 145-162.

[Clark01] L. Clark et al., "An embedded 32-b microprocessor core for low-power and high-performance applications," JSSC, vol. 36, no. 11, Nov. 2001, pp. 1599-1608.

[Clark02] L. Clark, S. Demmons, N. Deutscher, and F. Ricci, "Standby power management for a 0.18 mm microprocessor," Proc. Intl. Symp. Low Power Electronics and Design, Aug. 2002, pp. 7-12.

[Cobbold66] R. Cobbold, "Temperature effects on M.O.S. transistors," Electronics Letters, vol. 2, no. 6, Jun. 1966, pp. 190-192.

[Cobbold70] R. Cobbold, Theory and Application of Field Transistors, New York: Wiley Interscience, 1970.

[Colwell95] R. Colwell and R. Steck, "A 0.6 mm BiCMOS processor with dynamic execution," Proc. IEEE Solid-State Circuits Conf., 1995, pp. 176-177.

[Colwell06] R. Colwell, The Pentium Chronicles: The People, Passion, and Politics Behind Intel's Landmark Chips, New York: Wiley, 2006.

[Cooley07] J. Cooley, "Verilog vs. VHDL," www.deepchip.com/items/dvcon07-02.html, Apr. 2007.

[Cortadella92] J. Cortadella and J. Llaberia, "Evaluation of A+B=K conditions without carry propagation," IEEE Trans. Computers, vol. 41, no. 11, Nov. 1992, pp. 1484-1487.

[Crews03] M. Crews and Y. Yuenyongsgool, "Practical design for transferring signals between clock domains," EDN Magazine, Feb. 20, 2003, pp. 65-71.

[Curran02] B. Curran et al., "IBM eServer z900 high-frequency microprocessor technology, circuits, and design methodology," IBM J. Research and Development, vol. 46, no. 4/5, Jul./Sep. 2002, pp. 631-644.

[Dabral98] S. Dabral and T. Maloney, Basic ESD and I/O Design, New York: John Wiley & Sons, 1998.

[Dadda65] L. Dadda, "Some schemes for parallel multipliers," Alta Frequenza, vol. 34, no. 5, May 1965, pp. 349-356.

[Dally98] W. Dally and J. Poulton, Digital Systems Engineering, Cambridge, UK: Cambridge University Press, 1998.

[Das06] S. Das et al., "A self-tuning DVS processor using delay-error detection and correction," JSSC, vol. 41, no. 4, Apr. 2006, pp. 792-804.

[Das09] S. Das et al., "RazorII: in situ error detection and correction for PVT and SER tolerance," JSSC, vol. 44, no. 1, Jan. 2009, pp. 32-48.

[Davari99] B. Davari, "CMOS technology: present and future," Symp. VLSI Circuits Digest Tech. Papers, 1999, pp. 5-10.

[Davis69] R. Davis, "The ILLIAC IV processing element," IEEE Trans. Computers, vol. C-18, no. 9, Sep. 1969, pp. 800-816.

[Degalahal05] V. Degalahal, L. Li, V. Narayanan, M. Kandemir, and M. Irwin, "Soft errors issues in low-power caches," IEEE Trans. VLSI, vol. 13, no. 10, Oct. 2005, pp. 1157-1166.

[DeHon93] A. DeHon, T. Knight Jr., and T. Simon, "Automatic impedance control," Proc. Intl. Solid-State Circuits Conf., Feb. 1993, pp. 164-165, 283.

[Deleganes02] D. Deleganes, J. Douglas, B. Kommandur, and M. Patyra, "Designing a 3GHz, 130nm, Intel Pentium 4 processor," Symp. VLSI Circuits Digest Tech. Papers, 2002, pp. 130-133.

[Deleganes04] D. Deleganes et al., "LVS technology for the Intel Pentium 4 processor on 90nm technology," Intel Techology Journal, vol. 8, no. 1, Feb. 2004, pp. 43-53.

[Deleganes05] D. Deleganes et al., "Low-voltage swing logic circuits for a Pentium 4 processor integer core," JSSC, vol. 40, no. 1, Jan. 2005, pp. 36-43.

[Delgado-Frias00] J. Delgado-Frias and J. Nyathi, "A high-performance encoder with priority lookahead," IEEE Trans. Circuits and Systems I, vol. 47, no. 9, Sep. 2000, pp. 1390-1393.

[Dennard68] R. Dennard, "Field-effect transistor memory," US Patent 3,387,286, 1968.

[Dennard74] R. Dennard et al., "Design of ion-implanted MOSFET's with very small physical dimensions," JSSC, vol. SC-9, no. 5, Oct. 1974, pp. 256-268.

[Dhanesha95] H. Dhanesha, K. Falakshahi, and M. Horowitz, "Array-of-arrays architecture for parallel floating point multiplication," Proc. Conf. Advanced Research in VLSI, 1995, pp. 150-157.

[Dickson76] J. Dickson, "On-chip high-voltage generation in MNOS integrated circuits using an improved voltage multiplier technique," JSSC, vol. 11, no. 3, Jun. 1976, pp. 374-378.

[Dike99] C. Dike and E. Burton, "Miller and noise effects in a synchronizing flip-flop," JSSC, vol. 34, no. 6, Jun. 1999, pp. 849-855.

[Dobbalaere95] I. Dobbalaere, M. Horowitz, and A. El Gamal, "Regenerative feedback repeaters for programmable interconnect," JSSC, vol. 30, no. 11, Nov. 1995, pp. 1246-1253.

[Dobberpuhl92] D. Dobberpuhl et al., "A 200-MHz 64-b dual-issue CMOS microprocessor," JSSC, vol. 27, no. 11, Nov. 1992, pp. 1555-1567.

[Dobson95] J. Dobson and G. Blair, "Fast two's complement VLSI adder design," Electronics Letters, vol. 31, no. 20, Sep. 1995, pp. 1721-1722.

[Donnay03] S. Donnay and G. Gielen, eds., Substrate Noise Coupling in Mixed-Signal ASICs, Boston: Kluwer Academic Publishers, 2003.

[Donovan02] C. Donovan and M. Flynn, "A 'digital' 6-bit ADC in 0.25 mm CMOS," JSSC, vol. 37, no. 3, Mar. 2002, pp. 432-437.

[Doran88] R. Doran, "Variants of an improved carry look-ahead adder," IEEE Trans. Computers, vol. 37, no. 9, Sep. 1988, pp. 1110-1113.

[Doyle91] B. Doyle, B. Fishbein, and K. Mistry, "NBTI-enhanced hot carrier damage in p-channel MOSFETs," Proc. Intl. Electron Devices Meeting, 1991, pp. 529-532A.

[Drake07] A. Drake et al., "A distributed critical-path timing monitor for a 65nm high-performance microprocessor," Proc. Intl. Solid-State Circuits Conf., Feb. 2007, pp. 398-399.

[Draper97] D. Draper et al., "Circuit techniques in a 266-MHz MMX-enabled processor," JSSC, vol. 32, no. 11, Nov. 1997, pp. 1650-1664.

[Dunga07] M. Dunga et al., BSIM 4.6.1 MOSFET Model User's Manual, Department of Electrical Engineering and Computer Sciences, UC Berkeley, 2007.

[Earle65] J. Earle, "Latched carry-save adder," IBM Tech. Disclosure Bulletin, vol. 7, no. 10, Mar. 1965, pp. 909-910.

[Edwards93] B. Edwards, A. Corry, N. Weste, and C. Greenberg, "A single-chip video ghost canceller," JSSC, vol. 28, no. 3, Mar. 1993, pp. 379-383.

[Eichelberger78] E. Eichelberger and T. Williams, "A logic design structure for LSI testability," J. Design Automation and Fault Tolerant Computing, vol. 2, no. 2, May 1978, pp. 165-178.

[Elmore48] W. Elmore, "The transient response of damped linear networks with particular regard to wideband amplifiers," J. Applied Physics, vol. 19, no. 1, Jan. 1948, pp. 55-63.

[Emma08] P. Emma and E. Kursan, "Is 3D chip technology the next growth engine for performance improvement?" IBM J. Research & Dev., vol. 52, no. 6, Nov. 2008, pp. 541-552.

[EPA07] US Environmental Protection Agency, Report to Congress on Server and Data Center Energy Efficiency, Public Law 109-431, Aug. 2, 2007.

[Ercegovac89] M. Ercegovac and T. Lang, "Binary counter with counting period of one half adder independent of counter size," IEEE Trans. Circuits & Systems, vol. 36, no. 6, Jun. 1989, pp. 924-926.

[Ernst03] D. Ernst et al., "Razor: a low-power pipeline based on circuit-level timing speculation," Proc. Intl. Symp. Microarchitecture, Dec. 2003, pp. 7-18.

[Estreich82] D. Estreich and R. Dutton, "Modeling latch-up in CMOS integrated circuits," IEEE Trans. Computer-Aided Design, vol. CAD-1, no. 4, Oct. 1982, pp. 157-162.

[Evans95] R. Evans and P. Franzon, "Energy consumption modeling and optimization for SRAM's," JSSC, vol. 30, no. 5, May 1995, pp. 571-579.

[Faggin96] F. Faggin, M. Hoff, S. Mazor, and M. Shima, "The history of the 4004," IEEE Micro, vol. 16, no. 6, Dec. 1996, pp. 10-20.

[Fetzer02] E. Fetzer, M. Gibson, A. Klein, N. Calick, C. Zhu, E. Busta, and B. Mohammad, "A fully bypassed six-issue integer datapath and register file on the Itanium-2 microprocessor," JSSC, vol. 37, no. 11, Nov. 2002, pp. 1433-1440.

[Fetzer06] E. Fetzer, D. Dahle, C. Little, and K. Safford, "The parity protected, multithreaded register files on the 90-nm Itanium microprocessor," JSSC, vol. 41, no. 1, Jan. 2006, pp. 246-255.

[Fischer06] T. Fischer, J. Desai, B. Doyle, S. Naffziger, and B. Patella, "A 90-nm variable frequency clock system for a power-managed Itanium architecture processor," JSSC, vol. 41, no. 1, Jan. 2006, pp. 218-228.

[Fishburn85] J. Fishburn and A. Dunlop, "TILOS: A posynomial programming approach to transistor sizing," Proc. Intl. Conf. Computer-Aided Design, Nov. 1985, pp. 326-328.

[Flannagan85] S. Flannagan, "Synchronization reliability in CMOS technology," JSSC, vol. SC-20, no. 4, Aug. 1985, pp. 880-882.

[Foty96] D. Foty, MOSFET Modeling with SPICE: Principles and Practices, Upper Saddle River, NJ: Prentice Hall, 1996.

[Friedman84] V. Friedman and S. Liu, "Dynamic logic CMOS circuits," JSSC, vol. SC-19, no. 2, Apr. 1984, pp. 263-266.

[Frohman69] D. Frohman-Bentchkowsky and A. Grove, "Conductance of MOS transistors in saturation," IEEE Trans. Electron Devices, vol. ED-16, no. 1, Jan. 1969, pp. 108-113.

[Frowerk77] R. Frowerk, "Signature Analysis: A New Digital Field Service Method," Hewlett Packard Journal, May 1977, pp. 2-8.

[Fujiwara06] E. Fujiwara, Code Design for Dependable Systems: Theory and Practical Applications, New York: Wiley, 2006.

[Gabara92] T. Gabara and S. Knauer, "Digitally adjustable resistors in CMOS for high-performance applications," JSSC, vol. 27, no. 8, Aug. 1992, pp. 1176-1185.

[Gago93] A. Gago, R. Escano, and J. Hidalgo, "Reduced implementation of D-type DET flip-flops," JSSC, vol. 28, no. 3, Mar. 1993, pp. 400-402.

[Gajski83] D. Gajski and R. Kuhn, "New VLSI tools," Computer, vol. 16, no. 12, Dec. 1983, pp. 11-14.

[Galiay80] J. Galiay, Y. Crouzet, and M. Verginiault, "Physical versus logical fault models MOS LSI circuits: impact on their testability," IEEE Trans. Computers, vol. C-29, no. 6, Jun. 1980, pp. 527-531.

[Gauthier02] C. Gauthier and B. Amick, "Inductance: Implications and solutions for high-speed digital circuits: the chip electrical interface," Proc. IEEE Intl. Solid-State Circuits Conf., vol. 2, 2002, pp. 563-565.

[Geannopoulos98] G. Geannopoulos and X. Dai, "An adaptive digital deskewing circuit for clock distribution networks," Proc. IEEE Intl. Solid-State Circuits Conf., 1998, pp. 400-401.

[Gelsinger01] P. Gelsinger, "Microprocessors for the new millennium: challenges, opportunities, and new frontiers," Proc. IEEE Intl. Solid-State Circuits Conf., 2001, pp. 22-25.

[George96] S. George, A. Ott, and J. Klaus, "Surface chemistry for atomic layer growth," J. Phys. Chem., vol. 100, 1996, pp. 13121-13131.

[George07] V. George et al., "Penryn: 45-nm next generation Intel Core 2 processor," Proc. Intl. Solid-State Circuits Conf., Nov. 2007, pp. 14-17.

[Geppert04] L. Geppert, "Chip making's wet new world," IEEE Spectrum, vol. 41, no. 5, May 2004, pp. 29-33.

[Gerosa94] G. Gerosa et al., "A 2.2 W, 80 MHz superscalar RISC microprocessor," JSSC, vol. 29, no. 12, Dec. 1994, pp. 1440-1452.

[Gerosa09] G. Gerosa et al., "A sub-2 W low power IA processor for mobile internet devices in 45 nm high-k metal gate CMOS," JSSC, vol. 44, no. 1, Jan. 2009, pp. 73-82.

[Ginosar03] R. Ginosar, "Fourteen ways to fool your synchronizer," Proc. Intl. Symp. Asynchronous Circuits and Systems, May 2003, pp. 89-96.

[Glasser85] L. Glasser and D. Dobberpuhl, The Design and Analysis of VLSI Circuits, Reading, MA: Addison Wesley, 1985.

[Gochman03] S. Gochman et al., "The Intel Pentium M processor: microarchitecture and performance," Intel Technology Journal, vol. 7, no. 2, May 2003, pp. 21-36.

[Golden99] M. Golden et al., "A seventh-generation x86 microprocessor," JSSC, vol. 34, no. 11, Nov. 1999, pp. 1466-1477.

[Golomb81] S. Golomb, Shift Register Sequences, Revised Edition, Laguna Hills, CA: Aegean Park Press, 1981.

[Gonclaves83] N. Gonclaves and H. DeMan, "NORA: a racefree dynamic CMOS technique for pipelined logic structures," JSSC, vol. SC-18, no. 3, Jun. 1983, pp. 261-266.

[Gonzalez96] R. Gonzalez and M. Horowitz, "Energy dissipation in general purpose microprocessors," JSSC, vol. 31, no. 9, Sep. 1996, pp. 1277-1284.

[Gonzalez97] R. Gonzalez, B. Gordon, and M. Horowitz, "Supply and threshold voltage scaling for low power CMOS," JSSC, vol. 32, no. 8, Aug. 1997, pp. 1210-1216.

[Goto92] G. Goto, T. Sato, M. Nakajima, and T. Sukemura, "A 54x54-b regularly structured tree multiplier," JSSC, vol. 27, no. 9, Sep. 1992, pp. 1229-1236.

[Goto97] G. Goto et al., "A 4.1-ns compact 54x54-b multiplier utilizing sign-select Booth encoders," JSSC, vol. 32, no. 11, Nov. 1997, pp. 1676-1682.

[Grad04] J. Grad and J. Stine, "A hybrid Ling carry-select adder," Proc. Asilomar Conf. Signals, Systems, and Computers, Nov. 2004, pp. 1363-1367.

[Gray53] F. Gray, "Pulse code communications," US Patent 2,632,058, 1953.

[Gray01] P. Gray, P. Hurst, S. Lewis, and R. Meyer, Analysis and Design of Analog Integrated Circuits, 4th ed., New York: John Wiley & Sons, 2001.

[Greenhill97] D. Greenhill et al., "A 330 MHz 4-way superscalar microprocessor," Proc. Intl. Solid-State Circuits Conf., Feb. 1997, pp. 166-167, 449.

[Gregg07] J. Gregg and T. Chen, "Post silicon power/performance optimization in the presence of process variations using individual well-adaptive body biasing," IEEE Trans. VLSI, vol. 15, no. 3, Mar. 2007, pp. 366-376.

[Griffin83] W. Griffin and J. Hiltebeitel, "CMOS 4-way XOR circuit," IBM Technical Disclosure Bulletin, vol. 25, no. 11B, Apr. 1983, pp. 6066-6067.

[Gronowski96] P. Gronowski et al., "A 433-MHz 64-b quad-issue RISC microprocessor," JSSC, vol. 31, no. 11, Nov. 1996, pp. 1687-1696.

[Gronowski98] P. Gronowski, W. Bowhill, R. Preston, M. Gowan, and R. Allmon, "High-performance microprocessor design," JSSC, vol. 33, no. 5, May 1998, pp. 676-686.

[Grotjohn86] T. Grotjohn and B. Hoefflinger, "Sample-set differential logic (SSDL) for complex high-speed VLSI," JSSC, vol. SC-21, no. 2, Apr. 1986, pp. 367-369.

[Guilar09] N. Guilar, T. Kleeburg, A. Chen, D. Yankelevich, and R. Amirtharajah, "Integrated solar energy harvesting and storage," IEEE Trans. VLSI, vol. 17, no. 5, May 2009, pp. 627-637.

[Gunning92] B. Gunning, L. Yuan, T. Nguyen, and T. Wong, "A CMOS low-voltage-swing transmission-line transceiver," Proc. Intl. Solid-State Circuits Conf., Feb. 1992, pp. 58-59.

[Guo05] X. Guo and C. Sechen, "High speed redundant adder and divider in output prediction logic," Proc. Computer Society Symp. VLSI, May 2005, pp. 34-41.

[Gutierrez01] E. Gutierrez, J. Deen, and C. Claeys (eds.), Low Temperature Electronics: Physics, Devices, Circuits, and Applications, New York: Academic Press, 2001.

[Gutnik97] V. Gutnik and A. Chandrakasan, "Embedded power supply for low-power DSP," IEEE Trans. VLSI, vol. 5, no. 4, Dec. 1997, pp. 425-435.

[Guyot87] A. Guyot, B. Hochet, and J. Muller, "A way to build efficient carry-skip adders," IEEE Trans. Computers, vol. 36, no. 10, Oct. 1987, pp. 1144-1152.

[Guyot97] A. Guyot and S. Abou-Samra, "Modeling power consumption in arithmetic operators," Microelectronic Engineering, vol. 39, 1997, pp. 245-253.

[Hall00] S. Hall, G. Hall, and J. McCall, High-Speed Digital System Design, New York: Wiley, 2000.

[Hamada98] M. Hamada et al., "A top-down low power design technique using clustered voltage scaling with variable supply-voltage scheme," Proceedings of the IEEE, May 11-14, 1998, pp. 495-498.

[Hamming50] R. Hamming, "Error Detecting and Error Correcting Codes," Bell Systems Technical Journal, vol. 29, pp. 147-160.

[Hamzaoglu02] F. Hamzaoglu and M. Stan, "Circuit-level techniques to control gate leakage for sub-100 nm CMOS," Proc. Intl. Symp. Low Power Electronics and Design, 2002, pp. 60-63.

[Hamzaoglu09] F. Hamzaoglu et al., "A 3.8 GHz 153 Mb SRAM design with dynamic stability enhancement and leakage reduction in 45 nm high-k metal gate CMOS technology," JSSC, vol. 44, no. 1, Jan. 2009, pp. 148-154.

[Han87] T. Han and D. Carlson, "Fast area-efficient VLSI adders," Proc. IEEE Symp. Computer Arithmetic, 1987, pp. 49-56.

[Hanson06] S. Hanson et al., "Ultralow-voltage minimum-energy CMOS," IBM J. Research & Dev., vol. 50, no. 4/5, Jul./Sep. 2006, pp. 469-490.

[Hanson09] S. Hanson et al., "A low-voltage processor for sensing applications with picowatt standby mode," JSSC, vol. 44, no. 4, Apr. 2009, pp. 1145-1155.

[Harame01a] D. Harame and B. Meyerson, "The early history of IBM's SiGe mixed signal technology," IEEE Transactions on Electron Devices, vol. 48, no. 11, Nov. 2001, pp. 2555-2567.

[Harame01b] D. Harame et al., "Current status and future trends of SiGe BiCMOS technology," IEEE Transactions on Electron Devices, vol. 48, no. 11, Nov. 2001, pp. 2575-2594.

[Haring96] R. Haring et al., "Self-resetting logic register and incrementer," Symp. VLSI Circuits Digest Tech. Papers, 1996, pp. 18-19.

[Harris97] D. Harris and M. Horowitz, "Skew-tolerant domino circuits," JSSC, vol. 32, no. 11, Nov. 1997, pp. 1702-1711.

[Harris99] D. Harris, M. Horowitz, and D. Liu, "Timing analysis including clock skew," IEEE Trans. Computer-Aided Design, vol. 18, no. 11, Nov. 1999, pp. 1608-1618.

[Harris01a] D. Harris, Skew-Tolerant Circuit Design, San Francisco, CA: Morgan Kaufmann, 2001.

[Harris01b] D. Harris and S. Naffziger, "Statistical clock skew modeling with data delay variations," IEEE Trans. VLSI, vol. 9, no. 6, Dec. 2001, pp. 888-898.

[Harris03] D. Harris, "A taxonomy of prefix networks," Proc. 37th Asilomar Conf. Signals, Systems, and Computers, 2003, pp. 2213-2217.

[Harris04] D. Harris, "Logical effort of higher valency adders," Proc. Asilomar Conf. Signals, Systems, and Computers, Nov. 2004, pp. 1358-1362.

[Harris07] D. Harris and S. Harris, Digital Design and Computer Architecture, San Francisco: Morgan Kaufmann Publishers, 2007.

[Hart06] J. Hart et al., "Implementation of a fourth-generation 1.8-GHz dual-core SPARC V9 microprocessor," JSSC, vol. 41, no. 1, Jan. 2006, pp. 210-217.

[Hashemian92] R. Hashemian and C. Chen, "A new parallel technique for design of decrement/increment and two's complement circuits," Proc. IEEE Midwest Symp. Circuits and Systems, vol. 2, 1992, pp. 887-890.

[Hashimoto02] T. Hashimoto et al., "Integration of a 0.13-um CMOS and a high performance self-aligned SiGe HBT featuring low base resistance," Proc. Intl. Electron Devices Meeting, Dec. 2002, pp. 779-782.

[Hatamian86] M. Hatamian and G. Cash, "A 70-MHz 8-bit x 8-bit parallel pipelined multiplier in 2.5-mm CMOS," JSSC, vol. 21, no. 4, Aug. 1986, pp. 505-513.

[Haykin00] S. Haykin, Digital Communications, New York: John Wiley & Sons, 2000.

[Hazucha00] P. Hazucha, C. Svensson, and S. Wender, "Cosmic-ray soft error rate characterization of a standard 0.6-mm CMOS process," JSSC, vol. 35, no. 10, Oct. 2000, pp. 1422-1429.

[Hazucha04] P. Hazucha et al., "Measurements and analysis of SER-tolerant latch in a 90-nm dual-V_T CMOS process," JSSC, vol. 39, no. 9, Sep. 2004, pp. 1536-1543.

[Heald93] R. Heald and J. Holst, "A 6-ns cycle 256 kb cache memory and memory management unit," JSSC, vol. 28, no. 11, Nov. 1993, pp. 1078-1083.

[Heald98] R. Heald et al., "64-Kbyte sum-addressed-memory cache with 1.6-ns cycle and 2.6-ns latency," JSSC, vol. 33, no. 11, Nov. 1998, pp. 1682-1689.

[Heald00] R. Heald et al., "A third-generation SPARC v9 64-b microprocessor," JSSC, vol. 35, no. 11, Nov. 2000, pp. 1526-1538.

[Hedenstierna87] N. Hedenstierna and K. Jeppson, "CMOS circuit speed and buffer optimization," IEEE Trans. Computer-Aided Design, vol. CAD-6, no. 2, Mar. 1987, pp. 270-281.

[Heikes94] C. Heikes, "A 4.5mm² multiplier array for a 200MFLOP pipelined coprocessor," Proc. IEEE Intl. Solid-State Circuits Conf., 1994, pp. 290-291.

[Heller84] L. Heller, W. Griffin, J. Davis, and N. Thoma, "Cascode voltage switch logic: a differential CMOS logic family," Proc. IEEE Intl. Solid-State Circuits Conf., 1984, pp. 16-17.

[Hennessy90] J. Hennessy and D. Patterson, Computer Architecture: A Quantitative Approach, San Mateo, CA: Morgan Kaufmann Publishers, Inc., 1990.

[Heo02] S. Heo, K. Barr, M. Hampton, and K. Asanovic, "Dynamic fine-grain leakage reduction using leakage-biased bitlines," Proc. Intl. Symp. Computer Architecture, 2002, pp. 137-147.

[Hess94] C. Hess and L. Weiland, "Drop-in process control checkerboard test structure for efficient online process characterization and defect problem debugging," Proc. IEEE Int. Conf. Microelectronic Test Structures, vol. 7, Mar., 1994, pp. 152-159.

[Hicks08] J. Hicks, "45nm transistor reliability," Intel Technology Journal, vol. 12, no. 2, Jun. 2008, pp. 131-144.

[Hidaka89] H. Hidaka, K. Fujishima, Y. Matsuda, M. Asakura, and T. Yoshihara, "Twisted bit-line architectures for multi-megabit DRAM's," JSSC, vol. 24, no. 1, Feb. 1989, pp. 21-27.

[Hilewitz04] Y. Hilewitz, Z. Shi, and R. Lee, "Comparing fast implementations of bit permutation instructions," Proc. Asilomar Conf. Signals, Systems, and Computers, Nov. 2004, pp. 1856-1863.

[Hilewitz07] Y. Hilewitz and R. Lee, "Performing advanced bit manipulations efficiently in general-purpose processors," Proc. Computer Arithmetic Symp., June 2007, pp. 251-260.

[Hill68] C. Hill, "Noise margin and noise immunity in logic circuits," Microelectronics, vol. 1, Apr. 1968, pp. 16-21.

[Hinton01] G. Hinton et al., "A 0.18-mm CMOS IA-32 processor with a 4-GHz integer execution unit," JSSC, vol. 36, no. 11, Nov. 2001, pp. 1617-1627.

[Hisamoto98] D. Hisamoto et al., "A folded-channel MOSFET for deep-sub-tenth micron era," Tech. Digest Intl. Electron Devices Meeting, San Francisco, Dec. 1998, pp. 1032-1034.

[Ho01] R. Ho, K. Mai, and M. Horowitz, "The future of wires," Proc. IEEE, vol. 89, no. 4, Apr. 2001, pp. 490-504.

[Ho03a] R. Ho, K. Mai, and M. Horowitz, "Efficient on-chip global interconnects," Symp. VLSI Circuits Digest Tech. Papers, 2003, pp. 271-274.

[Ho03b] R. Ho, K. Mai, and M. Horowitz, "Managing wire scaling: a circuit perspective," Proc. IEEE Interconnect Technology Conf., 2003, pp. 177-179.

[Ho07] R. Ho, "Dealing with issues in VLSI interconnect scaling," Intl. Solid-State Circuits Conf. Tutorial, Feb. 2007.

[Hoeneisen72] B. Hoeneisen and C. Mead, "Fundamental limitations in Microelectronics-I. MOS technology," Solid-State Electronics, vol. 15, 1972, pp. 819-829.

[Hogge85] C. Hogge Jr., "A self correcting clock recovery circuit," IEEE Trans. Electron Devices, vol. 32, no. 12, Dec. 1985, pp. 2704-2706.

[Hook03] T. Hook et al., "Lateral ion implant straggle and mask proximity effect," IEEE Trans. Electron Devices, vol. 50, no. 9, Sep. 2003, pp. 1946-1951.

[Horowitz83] M. Horowitz and R. Dutton, "Resistance extraction from mask layout data," IEEE Trans. Computer-Aided Design, vol. CAD-2, no. 3, Jul. 1983, pp. 145-150.

[Horowitz87] M. Horowitz et al., "MIPS-X: a 20-MIPS peak, 32-bit microprocessor with on-chip cache," JSSC, vol. SC-22, no. 5, Oct. 1987, pp. 790-799.

[Horowitz04] M. Horowitz and W. Dally, "How scaling will change processor architecture," Proc. Intl. Solid-State Circuits Conf., Feb. 2004, pp. 132-133.

[Horstmann89] J. Horstmann, H. Eichel, and R. Coates, "Metastability behavior of CMOS ASIC flip-flops in theory and test," JSSC, vol. 24, no. 1, Feb. 1989, pp. 146-157.

[Hrishikesh02] M. Hrishikesh et al., "The optimal logic depth per pipeline stage is 6 to 8 FO4 inverter delays," Proc. Intl. Symp. Computer Architecture, 2002, pp. 14-24.

[Hsiao70] M. Hsiao, "A class of optimal minimum odd-weight-column SEC-DED codes," IBM J. Research & Dev., vol. 14, no. 4, Jul. 1970, pp. 395-401.

[Hsu91] W. Hsu, B. Sheu, and S. Gowda, "Design of reliable VLSI circuits using simulation techniques," JSSC, vol. 26, no. 3, Mar. 1991, pp. 452-457.

[Hsu92] W. Hsu, B. Sheu, S. Gowda, and C. Hwang, "Advanced integrated-circuit reliability simulation including dynamic stress effects," JSSC, vol. 27, no. 3, Mar. 1992, pp. 247-257.

[Hsu06a] S. Hsu et al., "A 110 GOPS/W 16-bit multiplier and reconfigurable PLA loop in 90-nm CMOS," JSSC, vol. 41, no. 1, Jan. 2006, pp. 256-264.

[Hsu06b] S. Hsu, A. Agarwal, M. Anders, S. Mathew, R. Krishnamurthy, and S. Borkar, "An 8.8GHz 198mW 16 x 64b 1R/1W variation tolerant register file in 65nm CMOS," Proc. Intl. Solid-State Circuits Conf., Feb. 2006, pp. 1785-1797.

[Hu90] Y. Hu and S. Chen, "GM_Plan: A Gate Matrix Layout Algorithm Based on Artificial Intelligence Planning Techniques," IEEE Trans. Computer-Aided Design, vol. 9, no. 8, Aug. 1990, pp. 836-845.

[Hu92] C. Hu, "IC Reliability Simulation," JSSC, vol. 27, no. 3, Mar. 1992, pp. 241-246.

[Hu95] C. Hu, K. Rodbell, T. Sullivan, K. Lee, and D. Bouldin, "Electromigration and stress-induced voiding in fine Al and Al-alloy thin-film lines," IBM J. Research and Development, vol. 39, no. 4, Jul. 1995, pp. 465-497.

[Huang00] Z. Huang and M. Ercegovac, "Effect of wire delay on the design of prefix adders in deep-submicron technology," Proc. 34th Asilomar Conf. Signals, Systems, and Computers, vol. 2, 2000, pp. 1713-1717.

[Huang02] C. Huang, J. Wang, and Y. Huang, "Design of high-performance CMOS priority encoders and incrementer/decrementers using multilevel lookahead and multilevel folding techniques," JSSC, vol. 37, no. 1, Jan. 2002, pp. 63-76.

[Huang03] X. Huang et al., "Loop-based interconnect modeling and optimization approach for multigigahertz clock network design," JSSC, vol. 38, no. 3, Mar. 2003, pp. 457-463.

[Huang05] Z. Huang and M. Ercegovac, "High-performance low-power left-to-right array multiplier design," IEEE Trans. Computers, vol. 54, no. 3, Mar. 2005, pp. 272-283.

[Huang06] A. Huang et al., "A 10Gb/s photonic modulator and WDM MUX/DEMUX integrated with electronics in 0.13/spl mu/m SOI CMOS," Proc. Intl. Solid-State Circuits Conf., Feb. 2006, pp. 922-929.

[Huh98] Y. Huh, Y. Sung, and S. Kang, "A study of hot-carrier-induced mismatch drift: a reliability issue for VLSI circuits," JSSC, vol. 33, no. 6, Jun. 1998, pp. 921-927.

[Huitema03] E. Huitema et al., "Plastic transistors in active-matrix displays," Proc. IEEE Intl. Solid-State Circuits Conf., Feb. 2003, pp. 380-381.

[Huntzicker08] S. Huntzicker, M. Dayringer, J. Soprano, A. Weerasinghe, D. Harris, and D. Patil, "Energy-delay tradeoffs in 32-bit static shifter designs," Proc. Intl. Conf. Computer Design, Oct. 2008, pp. 626-632.

[Hwang89] I. Hwang and A. Fisher, "Ultrafast compact 32-bit CMOS adders in multiple-output domino logic," JSSC, vol. 24, no. 2, Apr. 1989, pp. 358-369.

[Hwang99a] W. Hwang, R. Joshi, and W. Henkels, "A 500-MHz, 32-Word x 64-bit, eight-port self-resetting CMOS register file," JSSC, vol. 34, no. 1, Jan. 1999, pp. 56-67.

[Hwang99b] W. Hwang, G. Gristede, P. Sanda, S. Wang, and D. Heidel, "Implementation of a self-resetting CMOS 64-bit parallel adder with enhanced testability," JSSC, vol. 34, no. 8, Aug. 1999, pp. 1108-1117.

[Hwang02] D. Hwang, F. Dengwei, and A. Willson Jr, "A 400-MHz processor for the efficient conversion of rectangular to polar coordinates for digital communications applications," Symp. VLSI Circuits Digest Tech. Papers, Jun. 2002, pp. 248-251.

[ICKnowledge02] IC Knowledge, "Defect density trends," 2002, www.icknowledge.com/trends/defects.pdf.

[IEEE1076-08] IEEE Standard 1076-2008 (Revision of IEEE Standard 1076-2002), VHDL Language Reference Manual, 2009.

[IEEE1149.1-01] IEEE Standard 1149.1-2001, Test Access Port and Boundary-Scan Architecture, 2001.

[IEEE1364-01] IEEE Standard 1364-2001, Verilog Hardware Description Language, 2001.

[IEEE 1800-2009] IEEE Standard 1800-2009, System Verilog-Unified Hardware Design, Specification, and Verification Language, 2009.

[Intel10] Intel Corporation, Microprocessor Quick Reference Guide, www.intel.com/pressroom/kits/quickreffam.htm, 2010.

[Isaac08] R. Isaac, "The remarkable story of the DRAM industry," IEEE SSCS News, Winter 2008, pp. 45-49.

[Ishihara04] F. Ishihara, F. Sheikh, and B. Nikolic, "Level conversion for dual-supply systems," IEEE Trans. VLSI, vol. 12, no. 2, Feb. 2004, pp. 185-195.

[Ismail99] Y. Ismail, E. Friedman, and J. Neves, "Figures of merit to characterize the importance of on-chip interconnect," IEEE Trans. VLSI, vol. 7, no. 4, Dec. 1999, pp. 442-449.

[Itoh96] K. Itoh, A. Fridi, A. Bellaouar, and M. Elmasry, "A deep sub-V, single power-supply SRAM cell with multi-V_t, boosted storage node and dynamic load," Proc. VLSI Circuits Symp., Jun. 1996, pp. 132-133.

[Itoh97] K. Itoh, Y. Nakagome, S. Kimura, and T. Watanabe, "Limitations and challenges of multigigabit DRAM chip design," JSSC, vol. 32, no. 5, May 1997, pp. 624-634.

[Itoh01k] K. Itoh, VLSI Memory Chip Design, Berlin: Springer-Verlag, 2001.

[Itoh01n] N. Itoh et al., "A 600-MHz 54x54-bit multiplier with rectangular-styled Wallace tree," JSSC, vol. 36, no. 2, Feb. 2001, pp. 249-257.

[Itoh09] K. Itoh, "Adaptive circuits for the 0.5-V nanoscale CMOS era," Proc. Intl. Solid-State Circuits Conf., Feb. 2009, pp. 14-20.

[Jackson04] R. Jackson and S. Talwar, "High speed binary addition," Proc. Asilomar Conf. Signals, Systems, and Computers, Nov. 2004, pp. 1350-1353.

[Jacoboni77] C. Jacoboni, C. Canali, G. Ottaviani, and A. Alberigi Quaranta, "A review of some charge transport properties of silicon," Solid-State Electronics, vol. 20, 1977, pp. 77-89.

[Jayasumana91] A. Jayasumana, Y. Malaiya, and R. Rajsuman, "Design of CMOS circuits for stuck-open fault testability," JSSC, vol. 26, no. 1, Jan. 1991, pp. 58-61.

[Ji-ren87] Y. Ji-ren, I. Karlsson, and C. Svensson, "A true single-phase-clock dynamic CMOS circuit technique," JSSC, vol. SC-22, no. 5, Oct. 1987, pp. 899-901.

[Johnson88] M. Johnson, "A symmetric CMOS NOR gate for high-speed applications," JSSC, vol. SC-23, no. 5, Oct. 1988, pp. 1233-1236.

[Johnson91] B. Johnson, T. Quarles, A. Newton, D. Pederson, and A. Sangiovanni-Vincentelli, SPICE3 Version 3e User's Manual, UC Berkeley, Apr. 1991.

[Johnston96] A. Johnston, "The influence of VLSI technology evolution on radiation-induced latchup in space systems," IEEE Trans. Nuclear Science, vol. 43, no. 2, Apr. 1996, pp. 505-521.

[Josephson02] D. Josephson, "The manic depression of microprocessor debug," Proc. Intl. Test Conf., 2002, pp. 657-663.

[Jung01] S. Jung, S. Yoo, K. Kim, and S. Kang, "Skew-tolerant high-speed (STHS) domino logic," Proc. IEEE Intl. Symp. Circuits and Systems, 2001, pp. 154-157.

[Kahng08] A. Kahng and K. Samadi, "CMP fill synthesis: A survey of recent studies," IEEE Trans. CAD, vol. 27, no. 1, Jan. 2008, pp. 3-19.

[Kamon94] M. Kamon, J. Tsuk, and J. White, "FASTHENRY: a multipole-accelerated 3-D inductance extraction program," IEEE Trans. Microwave Theory and Techniques, vol. 42, no. 9, Sep. 1994, pp. 1750-1758.

[Kanamoto07] T. Kanamoto et al., "Impact of well edge proximity effect on timing," Proc. European Solid State Device Research Conf., Sep. 2007, pp. 115-118.

[Kanda02] K. Kanda, T. Miyazaki, M. Sik, H. Kawaguchi, and T. Sakurai, "Two orders of magnitude leakage power reduction of low voltage SRAMs by row-by-row dynamic V_DD control (RRDV) scheme," Proc. Intl. ASIC/SOC Conf., Sep. 2002, pp. 381-385.

[Kang03] S. Kang and Y. Leblebici, CMOS Digital Integrated Circuits, 3rd ed., Boston: McGraw Hill, 2003.

[Kanj06] R. Kanj, R. Joshi, and S. Nassif, "Mixture importance sampling and its application to the analysis of SRAM designs in the presence of rare failure events," Proc. Design Automation Conf., 2006, pp. 69-72.

[Kanno07] Y. Kanno et al., "Hierarchical power distribution with power tree in dozens of power domains for 90-nm low-power multi-CPU SoCs," JSSC, vol. 42, no. 1, Jan. 2007, pp. 74-83.

[Kantabutra91] V. Kantabutra, "Designing optimum carry-skip adders," Proc. IEEE Symp. Computer Arithmetic, 1991, pp. 146-153.

[Kantabutra93] V. Kantabutra, "A recursive carry-lookahead/carry-select hybrid adder," IEEE Trans. Computers, vol. 42, no. 12, Dec. 1993, pp. 1495-1499.

[Kapur02] P. Kapur, J. McVittie, and K. Saraswat, "Technology and reliability constrained future copper interconnects. I. Resistance modeling," IEEE Trans. Electron Devices, vol. 49, no. 4, Apr. 2002, pp. 590-597.

[Karnik01] T. Karnik, B. Bloechel, K. Soumyanath, V. De, and S. Borkar, "Scaling trends of cosmic rays induced soft errors in static latches beyond 0.18 m," Symp. VLSI Circuits Digest Tech. Papers, 2001, pp. 61-62.

[Kavaleros06] J. Kavalieros et al., "Tri-gate transistor architecture with high-k gate dielectrics, metal gates and strain engineering," Proc. VLSI Technology Symp., 2006, pp. 50-51.

[Keating07] M. Keating, D. Flynn, R. Aitken, A. Gibbons, and K. Shi, Low Power Methodology Manual, New York: Springer, 2007.

[Keeth07] B. Keeth, J. Baker, B. Johnson, F. Lin, DRAM Circuit Design: Fundamental and High-Speed Topics, IEEE Press, 2007.

[Keshavarzi01] A. Keshavarzi et al., "Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs," Proc. Intl. Symp. Low Power Electronics and Design, 2001, pp. 207-212.

[Keyes70] R. Keyes, E. Harris, and K. Konnerth, "The role of low temperatures in the operation of logic circuitry," Proc. IEEE, vol. 58, no. 12, Dec. 1970, pp. 1914-1932.

[Keyes75] R. Keyes, "The effect of randomness in the distribution of impurity atoms on FET thresholds," Applied Physics, 8, 1975, pp. 251-259.

[Khalil08] D. Khalil, M. Khellah, Nam-Sung Kim, Y. Ismail, T. Karnik, and V. De, "Accurate estimation of SRAM dynamic stability," IEEE Trans. VLSI, vol. 16, no. 12, Dec. 2008, pp. 1639-1647.

[Khare02] M. Khare et al., "A high performance 90nm SOI technology with 0.992 mm² 6T-SRAM cell," Proc. Intl. Electron Devices Meeting, 2002, pp. 407-410.

[Khellah06] M. Khellah et al., "Wordline & bitline pulsing schemes for improving SRAM cell stability in low-V_cc 65nm CMOS designs," Proc. VLSI Circuits Symp., 2006, pp. 9-10.

[Khellah07] M. Khellah et al., "A 256-Kb dual-VCC SRAM building block in 65-nm CMOS process with actively clamped sleep transistor," JSSC, vol. 42, no. 1, Jan. 2007, pp. 233-242.

[Khellah09] M. Khellah et al., "Process, temperature, and supply-noise tolerant 45 nm dense cache arrays with diffusion-notch-free (DNF) 6T SRAM cells and dynamic multi-Vcc circuits," JSSC, vol. 44, no. 4, Apr. 2009, pp. 1199-1208.

[Kielkowski95] R. Kielkowski, SPICE: Practical Device Modeling, Boston: McGraw-Hill, 1995.

[Kilburn59] T. Kilburn, D. Edwards, and D. Aspinall, "Parallel addition in digital computers-a new fast 'carryc circuit," Proc. IEE, vol. 106B, 1959, pp. 460-464.

[Kim00] J. Kim, Y. Jang, and H. Park, "CMOS sense amplifier-based flip-flop with two N-C2MOS output latches," Electronics Letters, vol. 36, no. 6, Mar. 16, 2000, pp. 498-500.

[Kim03] C. Kim, K. Roy, S. Hsu, A. Alvandpour, R. Krishnamurthy, and S. Borkar, "A process variation compensating technique for sub-90 nm dynamic circuits," Proc. VLSI Circuits Symp., Jun. 2003, pp. 205-206.

[Kim03b] J. Kim, M. Horowitz, and Gu-Yeon Wei, "Design of CMOS adaptive-bandwidth PLL/DLLs: a general approach," IEEE Trans. Circuits & Systems, vol. 50, no. 11, Nov. 2003, pp. 860-869.

[Kim05] C. Kim, J. Kim, S. Mukhopadhyay, and K. Roy, "A forward body-biased low-leakage SRAM cache: device, circuit and architecture considerations," IEEE Trans. VLSI, vol. 13, no. 3, Mar. 2005, pp. 349-357.

[Kim07] J. Kim, K. Jones, and M. Horowitz, "Variable domain transformation for linear PAC analysis of mixed-signal systems," Proc. Intl. Conf. Computer-Aided Design, Nov. 2007, pp. 887-894.

[Kim09] T. Kim, J. Liu, and C. Kim, "A voltage scalable 0.26 V, 64 kb 8T SRAM with V_min lowering techniques and deep sleep mode," JSSC, vol. 44, no. 6, Jun. 2009, pp. 1785-1795.

[Kinniment02] D. Kinniment and E. Chester, "Design of an on-chip random number generator using metastability," Proc. Intl. Solid-State Circuits Conf., Sep. 2002, pp. 595-598.

[Kio01] S. Kio, L. McMurchie, and C. Sechen, "Application of output prediction logic to differential CMOS," Proc. IEEE Computer Society Workshop on VLSI, 2001, pp. 57-65.

[Kitsukawa93] G. Kitsukawa et al., "256-Mb DRAM circuit technologies for file applications," JSSC, vol. 28, no. 11, Nov. 1993, pp. 1105-1113.

[Klass99] F. Klass et al., "A new family of semidynamic and dynamic flip-flops with embedded logic for high-performance processors," JSSC, vol. 34, no. 5, May 1999, pp. 712-716.

[Klaus98] J. Klaus, A. Ott, A. Dillon, and S. George, "Atomic layer controlled growth of Si₃N₄ films using sequential surface reactions," Surf. Sci., vol. 418, 1998, pp. L14-L19.

[Knebel98] D. Knebel et al., "Diagnosis and characterization of timing-related defects by time-dependent light emission," IEEE Intl. Test Conf., 1998, pp. 733-739.

[Knowles01] S. Knowles, "A family of adders," Proc. IEEE Symp. Computer Arithmetic, 2001, pp. 277-284.

[Koenemann79] B. Koenemann, J. Mucha, and G. Zwiehoff, "Built-in logic block observation techniques," Proc. Intl. Test Conf., Oct. 1979, pp. 37-41.

[Koester08] S. Koester et al., "Wafer-level 3D integration technology," IBM J. Research and Dev., vol. 52, no. 6, Nov. 2008, pp. 583-597.

[Kogge73] P. Kogge and H. Stone, "A parallel algorithm for the efficient solution of a general class of recurrence equations," IEEE Trans. Computers, vol. C-22, no. 8, Aug. 1973, pp. 786-793.

[Koh01] M. Koh et al., "Limit of gate oxide thickness scaling in MOSFETs due to apparent threshold voltage fluctuation induced by tunnel leakage current," IEEE Trans. Electron Devices, vol. 48, no. 2, Feb. 2001, pp. 259-264.

[Konstadinidis09] G. Konstadinidis et al., "Architecture and physical implementation of a third generation 65 nm, 16 core, 32 thread chip-multithreading SPARC processor," JSSC, vol. 44, no. 1, Jan. 2009, pp. 7-17.

[Kozu96] S. Kozu et al., "A 100 MHz 0.4W RISC processor with 200 MHz multiply-adder, using pulse-register technique," Proc. IEEE Intl. Solid-State Circuits Conf., 1996, pp. 140-141.

[Krambeck82] R. Krambeck, C. Lee, and H. Law, "High speed compact circuits with CMOS," JSSC, vol. SC-17, no. 3, Jun. 1982, pp. 614-619.

[Kuang05] J. Kuang et al., "A double-precision multiplier with fine-grained clock-gating support for a first-generation CELL processor," Proc. Intl. Solid-State Circuits Conf., Feb. 2005, pp. 378-605.

[Kulkarni04] S. Kulkarni and D. Sylvester, "High performance level conversion for dual V_DD design," IEEE Trans. VLSI, vol. 12, no. 9, Sep. 2004, pp. 926-936.

[Kumar94] R. Kumar, "ACMOS: an adaptive CMOS high performance logic," Electronics Letters, vol. 30, no. 6, Mar. 1994, pp. 483-484.

[Kumar01] R. Kumar, "Interconnect and noise immunity design for the Pentium 4 processor," Intel Technology Journal, vol. 5, no. 1, Q1 2001, pp. 1-12.

[Kumar06] R. Kumar and V. Kursun, "Reversed temperature-dependent propagation delay characteristics in nanometer CMOS circuits," IEEE Trans. Circuits & Systems, vol. 53, no. 10, Oct. 2006, pp. 1078-1082.

[Kumar09] R. Kumar and G. Hinton, "A family of 45nm IA processors," Proc. Intl. Solid-State Circuits Conf., Feb. 2009, pp. 58-59.

[Kuo01] J. Kuo and S. Lin, Low-Voltage SOI CMOS VLSI Devices and Circuits, New York: Wiley Interscience, 2001.

[Kurd01] N. Kurd, J. Barkarullah, R. Dizon, T. Fletcher, and P. Madland, "A multigigahertz clocking scheme for the Pentium 4 microprocessor," JSSC, vol. 36, no. 11, Nov. 2001, pp. 1647-1653.

[Kuroda96] T. Kuroda et al., "A 0.9-V, 150-MHz, 10-mW, 4 mm², 2-D discrete cosine transform core processor with variable threshold-voltage (VT) scheme," JSSC, vol. 31, no. 11, Nov. 1996, pp. 1770-1779.

[Kwong06] J. Kwong and A. Chandrakasan, "Variation-driven device sizing for minimum energy sub-threshold circuits," Proc. Intl. Symp. Low Power Electronics & Design, Oct. 2006, pp. 8-13.

[Kwong09] J. Kwong, Y. Ramadass, N. Verma, and A. Chandrakasan, "A 65 nm sub-V_t microcontroller with integrated SRAM and switched capacitor DC-DC converter," JSSC, vol. 44, no. 1, Jan. 2009, pp. 115-126.

[Kynett88] V. Kynett et al., "An in-system reprogrammable 256k CMOS flash memory," Proc. Intl. Solid-State Circuits Conf., Feb. 1988, pp. 132-133, 330.

[Ladner80] R. Ladner and M. Fischer, "Parallel prefix computation," J. ACM, vol. 27, no. 4, Oct. 1980, pp. 831-838.

[Lai97] F. Lai and W. Hwang, "Design and implementation of differential cascode voltage switch with pass-gate (DCVSPG) logic for high-performance digital systems," JSSC, vol. 32, no. 4, Apr. 1997, pp. 563-573.

[LaPedus07] M. LaPedus, "Costs cast ICs into Darwinian struggle," EE Times, Mar. 30, 2007.

[Larsson94] P. Larsson and C. Svensson, "Impact of clock slope on true single phase clocked (TSPC) CMOS circuits," JSSC, vol. 29, no. 6, Jun. 1994, pp. 723-726.

[Lasserre99] F. Lasserre et al., "Laser beam backside probing of CMOS integrated circuits," Microelectronics and Reliability, Jun. 1999, vol. 39, no. 6, pp. 957-961.

[Le06] T. Le, J. Han, A. von Jouanne, K. Mayaram, and T. Fiez, "Piezoelectric micro-power generation interface circuits," JSSC, vol. 41, no. 6, Jun. 2006, pp. 1411-1420.

[Leblebici96] Y. Leblebici, "Design considerations for CMOS digital circuits with improved hot-carrier reliability," JSSC, vol. 31, no. 7, Jul. 1996, pp. 1014-1024.

[Lee86] C. Lee and E. Szeto, "Zipper CMOS," IEEE Circuits and Systems Magazine, May 1986, pp. 10-16.

[Lee92] K. Lee and M. Breuer, "Design and test rules for CMOS circuits to facilitate IDDQ testing of bridging faults," IEEE Trans. On CAD of Integrated circuits, vol. 11, no. 5, May 1992, pp. 659-670.

[Lee98] M. Lee, "A multilevel parasitic interconnect capacitance modeling and extraction for reliable VLSI on-chip clock delay evaluation," JSSC, vol. 33, no. 4, Apr. 1998, pp. 657-661.

[Lee03] D. Lee, W. Kwong, D. Blaauw, and D. Sylvester, "Analysis and minimization techniques for total leakage considering gate oxide leakage," Proc. Design Automation Conf., Jun. 2003, pp. 175-180.

[Lee05] W. Lee et al., "High performance 65 nm SOI technology with enhanced transistor strain and advanced-low-K BEOL," Proc. Intl. Electron Devices Meeting, Dec. 2005.

[Lee06] L. Lee, D. Weinlader, and C.K. Yang, "A sub-10-ps multiphase sampling system using redundancy," JSSC, vol. 41, no. 1, Jan. 2006, pp. 265-273.

[Lehman61] M. Lehman and N. Burla, "Skip technique for high-speed carry-propagation in binary arithmetic units," IRE Trans. Electronic Computers, vol. 10, Dec. 1961, pp. 691-698.

[Leighton92] F. Leighton, Introduction to Parallel Algorithms and Architectures: Arrays; Trees; Hypercubes, San Francisco: Morgan Kaufmann, 1992.

[Leon07] A. Leon, K. Tam, J. Shin, D. Weisner, and F. Schumacher, "A power-efficient high-throughput 32-thread SPARC processor," JSSC, vol. 42, no. 1, Jan. 2007, pp. 7-16.

[Lhermet08] H. Lhermet, C. Condemine, M. Plissonnier, R. Salot, P. Audebert, and M. Rosset, "Efficient power management circuit: from thermal energy harvesting to above-IC microbattery energy storage," JSSC, vol. 43, no. 1, Jan. 2008, pp. 246-255.

[Liew90] B. Liew, N. Cheung, and C. Hu, "Projecting interconnect electromigration lifetime for arbitrary current waveforms," IEEE Trans. Electron Devices, vol. 37, no. 5, May 1990, pp. 1343-1351.

[Lih07] Y. Lih, N. Tzartzanis, and W. Walker, "A leakage current replica keeper for dynamic circuits," JSSC, vol. 42, no. 1, Jan. 2007, pp. 48-55.

[Lim72] R. Lim, "A barrel switch design," Computer Design, Aug. 1972, pp. 76-78.

[Lim05] D. Lim, J. Lee, B. Gassend, G. Suh, M. van Dijk, and S. Devadas, "Extracting secret keys from integrated circuits," IEEE Trans. VLSI, vol. 13, no. 10, Oct. 2005, pp. 1200-1205.

[Lin83] S. Lin and D. Costello, Error Control Coding: Fundamentals and Applications, Upper Saddle River, NJ: Prentice Hall, 1983.

[Linderman04] M. Linderman, D. Harris, and D. Diaz, "Bounding bus delay and noise effects of on-chip inductance," Proc. Workshop on Signal Propagation on Interconnects, May 2004, pp. 167-170.

[Ling81] H. Ling, "High-speed binary adder," IBM J. Research and Development, vol. 25, no. 3, May 1981, pp. 156-166.

[Liu01] X. Liu, C. Lee, C. Zhou, and J. Han, "Carbon nanotube field-effect inverters," Appl. Phys. Letters, vol. 79, no. 20, Nov. 2001, pp. 3329-3331.

[Lofstrom00] K. Lofstrom, W. Daasch, and D. Taylor, "IC identification circuit using device mismatch," Proc. Intl. Solid-State Circuits Conf., 2000, pp. 372-373.

[Lohstroh79] J. Lohstroh, "Static and dynamic noise margins of logic circuits," JSSC, vol. SC-14, no. 3, Jun. 1979, pp. 591-598.

[Lohstroh83] J. Lohstroh, E. Seevinck, and J. de Groot, "Worst-case static noise margin criteria for logic circuits and their mathematical equivalence," JSSC, vol. SC-18, no. 6, Dec. 1983, pp. 803-807.

[Lu88] S. Lu, "Implementation of iterative networks with CMOS differential logic," JSSC, vol. 23, no. 4, Aug. 1988, pp. 1013-1017.

[Lu91] S. Lu and M. Ercegovac, "Evaluation of two-summand adders implemented in ECDL CMOS differential logic," JSSC, vol. 26, no. 8, Aug. 1991, pp. 1152-1160.

[Lu93] F. Lu, H. Samueli, J. Yuan, and C. Svensson, "A 700 MHz 24-b pipelined accumulator in 1.2-um CMOS for application as a numerically controlled oscillator," JSSC, vol. 28, no. 8, Aug. 1993, pp. 878-886.

[Lu93b] F. Lu and H. Samueli, "A 200-MHz CMOS pipelined multiplier-accumulator using a quasi-domino dynamic full-adder cell design," JSSC, vol. 28, no. 2, Feb. 1993, pp. 123-132.

[Lu08] S. Lu, S. Hsu, and D. Somasekhar, "Memory arrays circuits for computer architects," IEEE Micro Tutorial, 2008.

[Lynch92] T. Lynch and E. Swartzlander, "A spanning tree carry lookahead adder," IEEE Trans. Computers, vol. 41, no. 8, Aug. 1992, pp. 931-939.

[Lyon87] R. Lyon and R. Schediwy, "CMOS static memory with a new four-transistor memory cell," Proc. Advanced Research in VLSI, Mar. 1987, pp. 111-132.

[Lyons62] R. Lyons and W. Vanderkulk, "The use of triple-modular redundancy to improve computer reliability," IBM Journal, Apr. 1962, pp. 200-209.

[Ma94] S. Ma and P. Franzon, "Energy control and accurate delay estimation in the design of CMOS buffers," JSSC, vol. 29, no. 9, Sep. 1994, pp. 1150-1153.

[Mack08] C. Mack, "Seeing double," IEEE Spectrum, vol. 45, no. 11, Nov. 2008, pp. 46-51.

[MacSorley61] O. MacSorley, "High-Speed arithmetic in binary computers," Proc. IRE, vol. 49, pt. 1, Jan. 1961, pp. 67-91.

[Mahalingam85] M. Mahalingam, "Thermal management in semiconductor device packages," Proc. IEEE Custom Integrated Circuits Conf., 1985, pp. 46-49.

[Mai05] K. Mai et al., "Architecture and circuit techniques for a 1.1-GHz 16-kb reconfigurable memory in 0.18-mm CMOS," JSSC, vol. 40, no. 1, Jan. 2005, pp. 261-275.

[Maier97] C. Maier et al., "A 533-MHz BiCMOS superscalar RISC microprocessor," JSSC, vol. 32, no. 11, Nov. 1997, pp. 1625-1634.

[Majerski67] S. Majerski, "On determination of optimal distributions of carry skips in adders," IEEE Trans. Electronic Computers, vol. EC-16, no. 1, 1967, pp. 45-58.

[Maksimovic00] D. Maksimovic, V. Oklobdzija, B. Nikolic, and K. Current, "Clocked CMOS adiabatic logic with integrated single-phase power-clock supply," IEEE Trans. VLSI, vol. 8, no. 4, Aug. 2000, pp. 460-463.

[Maluf04] N. Maluf and K. Williams, An Introduction to Microelectromechanical Systems, 2nd ed., Norwood, MA: Artech House, 2004.

[Maneatis03] J. Maneatis, I. McClatchie, J. Maxey, and M. Shankaradas, "Self-biased high-bandwidth low-jitter 1-to-4096 multiplier clock generator PLL," JSSC, vol. 38, no. 11, Nov. 2003, pp. 1795-1803.

[Markovic04] D. Markovic, V. Stojanovic, B. Nikolic, M. Horowitz, and R. Brodersen, "Methods for true energy-performance optimization," JSSC, vol. 39, no. 8, Aug. 2004, pp. 1282-1293.

[Masuoka84] F. Masuoka, M. Asano, H. Iwahashi, T. Komuro, and S. Tanaka, "A new flash E2PROM cell using triple polysilicon technology," Proc. Intl. Electron Devices Meeting, 1984, pp. 464-467.

[Masuoka87] F. Masuoka, M. Momodomi, Y. Iwata, and R. Shirota, "New ultra high density EPROM and flash EEPROM with NAND structure cell," Proc. Intl. Electron Devices Meeting, 1987, pp. 552-555.

[Mathew03] S. Mathew, M. Anders, R. Krishnamurthy, and S. Borkar, "A 4-GHz 130-nm address generation unit with 32-bit sparse-tree adder core," JSSC, vol. 38, no. 5, May 2003, pp. 689-695.

[Mathew05] S. Mathew, M. Anders, B. Bloechel, Trang Nguyen, R. Krishnamurthy, and S. Borkar, "A 4-GHz 300-mW 64-bit integer execution ALU with dual supply voltages in 90-nm CMOS," JSSC, vol. 40, no. 1, Jan. 2005, pp. 44-51.

[Matsui94] M. Matsui et al., "A 200 MHz 13 mm² 2-D DCT macrocell using sense-amplifier pipeline flip-flop scheme," JSSC, vol. 29, no. 12, Dec. 1994, pp. 1482-1490.

[May79] T. May and M. Woods, "Alpha-particle-induced soft errors in dynamic memories," IEEE Trans. Electron Devices, vol. ED-26, no. 1, Jan. 1979, pp. 2-9.

[McGowen06] R. McGowen et al., "Power and temperature control on a 90-nm Itanium family processor," JSSC, vol. 41, no. 1, Jan. 2006, pp. 229-237.

[McMurchie00] L. McMurchie, S. Kio, G. Yee, T. Thorp, and C. Sechen, "Output prediction logic: a high-performance CMOS design technique," Proc. Intl. Conf. Computer Design, 2000, pp. 247-254.

[Mead80] C. Mead and L. Conway, Introduction to VLSI Systems, Reading, MA: Addison-Wesley, 1980.

[Mears96] J. Mears, "Transmission line RAPIDDESIGNER operation and applications guide," National Semiconductor Application Note 905, May 1996, www.national.com/an/AN/AN-905.pdf.

[Mehta99] G. Mehta, D. Harris, and D. Singh, "Pulsed Domino Latches," US Patent 5,880,608, 1999.

[Meier99] N. Meier, T. Marieb, P. Flinn, R. Gleixner, and J. Bravman, "In-situ studies of electromigration voiding in passivated copper interconnects," AIP Conf. Proc. 491, Fifth Intl. Workshop on Stress-Induced Phenomena in Metallization, Jun. 1999, p. 180.

[Meijs84] N. van der Meijs and J. Fokkema, "VLSI circuit reconstruction from mask topology," Integration, TheVLSI Journal, vol. 2, no. 2, Jun. 1984, pp. 85-119.

[Meindl00] J. Meindl and J. Davis, "The fundamental limit on binary switching energy for terascale integration (TSI)," JSSC, vol. 35, no. 10, Oct. 2000, pp. 1515-1516.

[Meng08] X. Meng, R. Saleh, and K. Arabi, "Layout of decoupling capacitors in IP blocks for 90-nm CMOS," IEEE Trans. VLSI, vol. 16, no. 11, Nov. 2008, pp. 1581-1588.

[Merchant01] S. Merchant, S. Kang, M. Sanganeria, B. van Schravendijk, and T. Mountsier, "Copper interconnects for semiconductor devices," JOM: Journal of the Minerals, Metals, and Materials Society, vol. 53, no. 6, Jun. 2001, pp. 43-48.

[Messerschmitt90] D. Messerschmitt, "Synchronization in digital system design," IEEE J. Selected Areas Communications, vol. 8, no. 8, Oct. 1990, pp. 1404-1419.

[Min06] K. Min, H. Choi, H. Choi, H. Kawaguchi, and T. Sakurai, "Leakage-suppressed clock-gating circuit with Zigzag Super Cut-off CMOS (ZSCCMOS) for leakage-dominant sub-70-nm and sub-1-V-V_DD LSIs," IEEE Trans. VLSI, vol. 14, no. 4, Apr. 2006, pp. 430-435.

[Misaka96] A. Misaka, A. Goda, K. Matsuoka, H. Umimoto, and S. Odanaka, "A statistical critical dimension control at CMOS cell level," Proc. Intl. Electron Devices Meeting, Dec. 1996, pp. 631-634.

[Mistry07] K. Mistry et al., "A 45nm logic technology with high-k+ metal gate transistors, strained silicon, 9 Cu interconnect layers, 193nm dry patterning, and 100% Pb-free packaging," Proc. Intl. Electron Devices Meeting, Dec. 2007, pp. 247-250.

[Mitra05] S. Mitra, T. Karnik, N. Seifert, and Ming Zhang, "Logic soft errors in sub-65nm technologies design and CAD challenges," Proc. Design Automation Conf., Jun. 2005, pp. 2-4.

[Mizuno94] T. Mizuno, J. Okumtura, and A. Toriumi, "Experimental study of threshold voltage fluctuation due to statistical variation of chanel dopant number in MOSFET's," IEEE Trans. Electron Devices, vol. 41, no. 11, Nov. 1994, pp. 2216-2221.

[Moazzami90] R. Moazzami and C. Hu, "Projecting gate oxide reliability and optimizing reliability screens," IEEE Trans. Electron Devices, vol. 37, no. 7, Jul. 1990, pp. 1643-1650.

[Monsieur01] F. Monsieur, E. Vincent, D. Roy, S. Bruyre, G. Pananakakis, and G. Ghibaudo, "Time to breakdown and voltage to breakdown modeling for ultra-thin oxides (Tox<32A)," Proc. Intl. Integrated Reliability Workshop, 2001, pp. 20-25.

[Montanaro96] J. Montanaro et al., "A 160-MHz, 32-b, 0.5-W CMOS RISC microprocessor," JSSC, vol. 31, no. 11, Nov. 1996, pp. 1703-1714.

[Montoye90] R. Montoye, P. Cook, E. Hokenek, and R. Havreluk, "An 18 ns 56-bit multiply-adder circuit," Proc. Intl. Solid-State Circuits Conf., Feb. 1990, pp. 46-47.

[Moon08] P. Moon et al., "Process and electrical results for the on-die interconnect stack for Intel's 45nm process generation," Intel Technology Journal, vol. 12, no. 2, Jun. 2008, pp. 87-92.

[Moore65] G. Moore, "Cramming more components onto integrated circuits," Electronics, vol. 38, no. 8, Apr. 1965.

[Moore03] G. Moore, "No exponential is forever: but 'forever' can be delayed!" Proc. IEEE Intl. Solid-State Circuits Conf., 2003, pp. 1-19.

[Morgan59] C. Morgan and D. Jarvis, "Transistor logic using current switching routing techniques and its application to a fast carry-propagation adder," Proc. IEE, vol. 106B, 1959, pp. 467-468.

[Morgenshtein09] A. Morgenshtein, E. Friedman, R. Ginosar, and A. Kolodny, "Unified logical effort-a method for delay evaluation and minimization in logic paths with RC interconnect," to appear in IEEE Trans. VLSI, 2010.

[Mori91] J. Mori et al., "A 10 ns 54x54 b parallel structured full array multiplier with 0.5 um CMOS technology," JSSC, vol. 26, no. 4, Apr. 1991, pp. 600-606.

[Morita06] Y. Morita et al., "A V_th-variation-tolerant SRAM with 0.3-V minimum operation voltage for memory-rich SoC under DVS environment," Proc. VLSI Circuits Symp., 2006, pp. 13-14.

[Morrison61] P. Morrison and E. Morrison, eds., Charles Babbage: On the Principles and Development of the Calculator, New York: Dover, 1961.

[Morton99] S. Morton, "On-chip inductance issues in multiconductor systems," Proc. Design Automation Conf., 1999, pp. 921-926.

[Mou90] Z. Mou and F. Jutand, "A class of close-to-optimum adder trees allowing regular and compact layout," Proc. IEEE Intl. Conf. on Computer Design, 1990, pp. 251-254.

[Mukhopadhyay03] S. Mukhopadhyay, C. Neau, R. Cakici, A. Agarwal, C. Kim, and K. Roy, "Gate leakage reduction for scaled devices using transistor stacking," IEEE Trans. VLSI, vol. 11, no. 4, Aug. 2003, pp. 716-730.

[Mukhopadhyay05] S. Mukhopadhyay, A. Raychowdhury, and K. Roy, "Accurate estimation of total leakage in nanometer-scale bulk CMOS circuits based on device geometry and doping profile," IEEE Trans. CAD, vol. 24, no. 3, Mar. 2005, pp. 363-381.

[Mule02] A. Mule, E. Glytsis, T. Gaylord, and J. Meindl, "Electrical and optical clock distribution networks for gigascale microprocessors," IEEE Trans. VLSI, vol. 10, no. 5, Oct. 2002, pp. 582-594.

[Muller03] R. Muller, T. Kamins, and M. Chan, Device Electronics for Integrated Circuits, 3rd ed., New York: John Wiley & Sons, 2003.

[Muller08] M. Muller, "Embedded processing at the heart of life and style," Proc. Intl. Solid-State Circuits Conf., Feb. 2008, pp. 32-37.

[Murabayashi96] F. Murabayashi et al., "2.5 V CMOS circuit techniques for a 200 MHz superscalar RISC processor," JSSC, vol. 31, no. 7, Jul. 1996, pp. 972-980.

[Mutoh95] S. Mutoh et al., "1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS," JSSC, vol. 30, no. 8, Aug. 1995, pp. 847-854.

[Mutoh99] S. Mutoh, S. Shigematsu, Y. Gotoh, and S. Konaka, "Design method of MTCMOS power switch for low-voltage high-speed LSIs," Proc. Design Automation Conf., Jan. 1999, pp. 113-116.

[Myny09] K. Myny et al., "A 128b organic RFID transponder chip, including Manchester encoding and ALOHA anti-collision protocol, operating with a data rate of 1529b/s," Proc. Intl. Solid-State Circuits Conf., Feb. 2009, pp. 206-207.

[Na02] M. Na, E. Nowak, W. Haensch, and J. Cai, "The effective drive current in CMOS inverters," Proc. Intl. Electron Devices Meeting, 2002, pp. 121-124.

[Nabors92] K. Nabors, S. Kim, and J. White, "Fast capacitance extraction of general three-dimensional structures," IEEE Trans. Microwave Theory and Techniques, vol. 40, no. 7, Jul. 1992, pp. 1496-1506.

[Nadig77] H. Nadig, "Signature analysis-concepts, examples and guidelines," Hewlett Packard Journal, vol. 28, no. 9, May 1977, pp. 15-21.

[Naffziger96] S. Naffziger, "A subnanosecond 0.5mm 64b adder design," Proc. IEEE Intl. Solid-State Circuits Conf., 1996, pp. 362-363.

[Naffziger98] S. Naffziger, "High speed addition using Ling's equations and dynamic CMOS logic," US Patent 5,719,803, 1998.

[Naffziger02] S. Naffziger, G. Colon-Bonet, T. Fischer, R. Riedlinger, T. Sullivan, and T. Grutkowski, "The implementation of the Itanium 2 microprocessor," JSSC, vol. 37, no. 11, Nov. 2002, pp. 1448-1460.

[Naffziger06] S. Naffziger et al., "The implementation of a 2-core, multi-threaded Itanium family processor," JSSC, vol. 41, no. 1, Jan. 2006, pp. 197-209.

[Naffziger06b] S. Naffziger, "High-performance processors in a power-limited world," Proc. VLSI Circuits Symp., 2006, pp. 93-97.

[Nagel75] L. Nagel, SPICE2: a computer program to simulate semiconductor circuits, Memo ERL-M520, Dept. of Electrical Engineering and Computer Science, University of California at Berkeley, May 9, 1975.

[Najm07] F. Najm, N. Menezes, and I. Ferzli, "A yield model for integrated circuits and its application to statistical timing analysis," IEEE Trans. CAD, vol. 26, no. 3, Mar. 2007, pp. 574-591.

[Nakagome03] Y. Nakagome, M. Horiguchi, T. Kawahara, and K. Itoh, "Review and future prospects of low-voltage RAM circuits," IBM J. Research and Dev., vol. 47, no. 5/6, Sep./Nov. 2003, pp. 525-552.

[Nalamalpu02] A. Nalamalpu, S. Srinivasan, and W. Burleson, "Boosters for driving long on-chip interconnects-design issues, interconnect synthesis, and comparison with repeaters," IEEE Trans. Computer-Aided Design, vol. 21, no. 1, Jan. 2002, pp. 50-62.

[Nambu98] H. Nambu et al., "A 1.8-ns access, 550-MHz, 4.5-Mb CMOS SRAM," JSSC, vol. 33, no. 11, Nov. 1998, pp. 1650-1658.

[Narasimha06] S. Narasimha et al., "High performance 45-nm SOI technology with enhanced strain, porous low-k BEOL, and immersion lithography," Proc. Intl. Electron Devices Meeting, Dec. 2006, pp. 1-4.

[Narayanan96] V. Narayanan, B. Chappell, and B. Fleischer, "Static timing analysis for self-resetting circuits," Proc. Intl. Conf. Computer-Aided Design, 1996, pp. 119-126.

[Narendra99] S. Narendra, D. Antoniadis, and V. De, "Impact of using adaptive body bias to compensate die-to-die V_t variation on within-die V_t variation," Proc. Intl. Symp. Low Power Electronics and Design, 1999, pp. 229-232.

[Narendra01] S. Narendra, S. Borkar, V. De, D. Antoniadis, and A. Chandrakasan, "Scaling of stack effect and its application for leakage reduction," Proc. Intl. Symp. Low Power Electronics and Design, 2001, pp. 195-200.

[Narendra03] S. Narendra, A. Keshavarzi, B. Bloechel, S. Borkar, and V. De, "Forward body bias for microprocessors in 130-nm technology generation and beyond," JSSC, vol. 38, no. 5, May 2003, pp. 696-701.

[Narendra06] S. Narendra and A. Chandrakasan, Leakage in Nanometer CMOS Technologies, New York: Springer, 2006.

[Natarajan08] S. Natarajan et al., "A 32 nm logic technology featuring 2nd-generation high-k+ metal-gate transistors, enhanced channel strain and 0.171 mm² SRAM cell size in a 291 Mb array," Proc. Intl. Electron Devices Meeting, Dec. 2008, pp. 1-3.

[National08] National Semiconductor, LVDS Owner's Manual, 4th ed., 2008, www.national.com/LVDS.

[Nawathe08] U. Nawathe, M. Hassan, K. Yen, A. Kumar, A. Ramachandran, and D. Greenhill, "Implementation of an 8-core, 64-thread, power-efficient SPARC server on a chip," JSSC, vol. 43, no. 1, Jan. 2008, pp. 6-20.

[Needham98] W. Needham, C. Prunty, and E. Yeoh, "High volume microprocessor test escapes, an analysis of defects our tests are missing," Proc. Intl. Test Conf., 1998, pp. 25-34.

[Ng96] P. Ng, P. Balsara, and D. Steiss, "Performance of CMOS differential circuits," JSSC, vol. 31, no. 6, Jun. 1996, pp. 841-846.

[Nii04] K. Nii et al., "A 90-nm low-power 32-kB embedded SRAM with gate leakage suppression circuit for mobile applications," JSSC, vol. 39, no. 4, Apr. 2004, pp. 684-693.

[Nikolić00] B. Nikolić, V. Oklobdzija, V. Stojanović, W. Jia, J. Chiu, and M. Leung, "Improved sense-amplifier-based flip-flop: design and measurements," JSSC, vol. 35, no. 6, Jun. 2000, pp. 876-884.

[NIST02] National Institute of Standards and Technology, "Security requirements for cryptographic modules," FIPS 140-2, 2001.

[Noguchi07] K. Noguchi and M. Nagata, "An on-chip multichannel waveform monitor for diagnosis of systems-on-a-chip integration," IEEE Trans. VLSI, vol. 15, no. 10, Oct. 2007, pp. 1101-1110.

[Noice83] D. Noice, A clocking discipline for two-phase digital integrated circuits, Stanford University Technical Report, Jan. 1983.

[Northrop99] G. Northrop et al., "609 MHz G5 S/399 microprocessor," Proc. Intl. Solid-State Circuits Conf., 1999, pp. 88-89.

[Nose00a] K. Nose and T. Sakurai, "Analysis and future trend of short-circuit power," IEEE Trans. CAD, vol. 19, no. 9, Sep. 2000, pp. 1023-1030.

[Nose00b] K. Nose, Soo-Ik Chae, and T. Sakurai, "Voltage dependent gate capacitance and its impact in estimating power and delay of CMOS digital circuits with low supply voltage," Proc. Intl. Symp. Low Power Electronics & Design, 2000, pp. 228-230.

[Nose00c] K. Nose and T. Sakurai, "Optimization of V_DD and V_TH for low-power and high-speed applications," Proc. Design Automation Conf., 2000, pp. 469-474.

[Nose06] K. Nose, M. Kajita, and M. Mizuno, "A 1ps-resolution jitter-measurement macro using interpolated jitter oversampling," Proc. Intl. Solid-State Circuits Conf., Feb. 2006, pp. 2112-2121.

[Nowka98] K. Nowka and T. Galambos, "Circuit design techniques for a gigahertz integer microprocessor," Proc. Intl. Conf. Computer Design, 1998, pp. 11-16.

[Oh06] H. Oh et al., "A fully pipelined single-precision floating-point unit in the synergistic processor element of a CELL processor," JSSC, vol. 41, no. 4, Apr. 2006, pp. 759-771.

[Ohbayashi07] S. Ohbayashi et al., "A 65-nm SoC embedded 6T-SRAM designed for manufacturability with read and write operation stabilizing circuits," JSSC, vol. 42, no. 4, Apr. 2007, pp. 820-829.

[Ohkubo95] N. Ohkubo et al., "A 4.4 ns CMOS 54x54-b multiplier using pass-transistor multiplexer," JSSC, vol. 30, no. 3, Mar. 1995, pp. 251-257.

[Oklobdzija85] V. Oklobdzija and E. Barnes, "Some optimal schemes for ALU implementation in VLSI technology," Proc. Computer Arithmetic Symp., 1985, pp. 137-143.

[Oklobdzija86] V. Oklobdzija and R. Montoye, "Design-performancce trade-offs in CMOS-domino logic," JSSC, vol. SC-21, no. 2, April 1986, pp. 304-309.

[Oklobdzija96] V. Oklobdzija, D. Villeger, and S. Liu, "A method for speed optimized partial product reduction and generation of fast parallel multipliers using an algorithmic approach ," IEEE Trans. Computers, vol. 45, no. 3, Mar. 1996, pp. 294-306.

[Oklobdzija05] V. Oklobdzija, B. Zeydel, H. Dao, S. Mathew, and R. Krishnamurthy, "Comparison of high-performance VLSI adders in the energy-delay space," IEEE Trans. VLSI, vol. 13, no. 6, Jun. 2005, pp. 754-758.

[Ortiz-Conde02] A. Ortiz-Conde, F. Sanchez, J. Liou, A. Cerdeira, M. Estrada, and Y. Yue, "A review of recent MOSFET threshold voltage extraction methods," Microelectronics Reliability, vol. 42, 2002, pp. 583-596.

[Osada01] K. Osada et al., "Universal-V_DD 0.65-2.0-V 32-kB cache using a voltage-adapted timing-generation scheme and a lithographically symmetrical cell," JSSC, vol. 36, no. 11, Nov. 2001, pp. 1738-1744.

[Osada04] K. Osada, K. Yamaguchi, Y. Saitoh, and T. Kawahara, "SRAM immunity to cosmic-ray-induced multierrors based on analysis of an induced parasitic bipolar effect," JSSC, vol. 39, no. 5, May 2004, pp. 827-833.

[Osada06] K. Osada, "Reviews and prospects of nanoscale SRAMs," Proc. Intl Conf. Integrated Circuit Design & Tech., 2006, pp. 1-8.

[Pagiamtzis06] K. Pagiamtzis and A. Sheikholeslami, "Content-addressable memory (CAM) circuits and architectures: a tutorial and survey," JSSC, vol. 41, no. 3, Mar. 2006, pp. 712-727.

[Paik96] W. Paik, H. Ki, and S. Kim, "Push-pull pass-transistor logic family for low voltage and low power," Proc. 22nd European Solid-State Circuits Conf., 1996, pp. 116-119.

[Paik08] P. Paik, V. Pamula, and K. Chakrabarty, "Adaptive cooling of integrated circuits using digital microfluidics," IEEE Trans. VLSI, vol. 16, no. 4, Apr. 2008, pp. 432-443.

[Parameswar96] A. Parameswar, H. Hara, and T. Sakurai, "A swing restored pass-transistor logic-based multiply and accumulate circuit for multimedia applications," JSSC, vol. 31, no. 6, Jun. 1996, pp. 804-809.

[Paraskevopoulos87] D. Paraskevopoulos and C. Fey, "Studies in LSI technology economics III: design schedules for application-specific integrated circuits," JSSC, vol. SC-22, no. 2, Apr. 1987, pp. 223-229.

[Park00] J. Park, H. Ngo, J. Silberman, and S. Dhong, "470 ps 64-bit parallel binary adder," Proc. VLSI Circuits Symp., 2000, pp. 192-193.

[Parker03] K. Parker, The Boundary-Scan Handbook, Boston: Kluwer Academic Publishers, 2003.

[Partovi96] H. Partovi et al., "Flow-through latch and edge-triggered flip-flop hybrid elements," Proc. IEEE Intl. Solid-State Circuits Conf., 1996, pp. 138-139.

[Pasternak87] J. Pasternak, A. Shubat, and C. Salama, "CMOS differential pass-transistor logic design," JSSC, vol. SC-22, no. 2, Apr. 1987, pp. 216-222.

[Pasternak91] J. Pasternak and C. Salama, "Design of submicrometer CMOS differential pass-transistor logic circuits," JSSC, vol. 26, no. 9, Sep. 1991, pp. 1249-1258.

[Patil07] D. Patil, O. Azizi, M. Horowitz, R. Ho, and R. Ananthraman, "Robust energy-efficient adder topologies," Proc. Computer Arithmetic Symp., Jun. 2007, pp. 16-28.

[Patil09] N. Patil, Jie Deng, S. Mitra, and H. Wong, "Circuit-level performance benchmarking and scalability analysis of carbon nanotube transistor circuits," IEEE Trans. Nanotechnology, vol. 8, no. 1, Jan. 2009, pp. 37-45.

[Patterson04] D. Patterson and J. Hennessy, Computer Organization and Design, 3rd ed., San Francisco, CA: Morgan Kaufmann, 2004.

[Paul02] B. Paul and K. Roy. Testing cross-talk induced delay faults in static CMOS circuit through dynamic timing analysis. Proc. Intl. Test Conf., Oct. 2002, pp. 384-390.

[Paul07] B. Paul, Kunhyuk Kang, H. Kufluoglu, M. Alam, and K. Roy, "Negative bias temperature instability: estimation and design for improved reliability of nanoscale circuits," IEEE Trans. CAD, vol. 26, no. 4, Apr. 2007, pp. 743-751.

[Pedroni10] V. Pedroni, Circuit Design and Simulation with VHDL, 2nd ed., Cambridge, MA: MIT Press, 2010.

[Pelgrom89] M. Pelgrom, A. Duinmaijer, and A. Welbers, "Matching properties of MOS transistors," JSSC, vol. 24, no. 5, Oct. 1989, pp. 1433-1440.

[Peng02] C. Peng et al., "A 90 nm generation copper dual damascene technology with ALD TaN barrier," Tech. Digest Intl. Electron Devices Meeting, Dec. 2002, pp. 603-606.

[Penney72] W. Penney and L. Lau, MOS Integrated Circuits, New York: Van Nostrand Reinhold, 1972.

[Perry05] D. Perry and H. Foster, Applied Formal Verification, New York: McGraw-Hill, 2005.

[Pertijs06] M. Pertijs and J. Huijsing, Precision Temperature Sensors in CMOS Technology, New York: Springer, 2006.

[Petegem94] W. van Petegem, B. Geeraerts, W. Sansen, and B. Graindourze, "Electrothermal simulation and design of integrated circuits," JSSC, vol. 29, no. 2, Feb. 1994, pp. 143-146.

[Pfennings85] L. Pfennings, W. Mol, J. Bastiens, and J. van Dijk, "Differential split-level CMOS logic for subnanosecond speeds," JSSC, vol. SC-20, no. 5, Oct. 1985, pp. 1050-1055.

[Pham06] D. Pham et al., "Overview of the architecture, circuit design, and physical implementation of a first-generation cell processor," JSSC, vol. 41, no. 1, Jan. 2006, pp. 179-196.

[Pihl98] J. Pihl, "Single-ended swing restoring pass transistor cells for logic synthesis and optimization," Proc. IEEE Intl. Symp. Circuits and Systems, vol. 2, 1998, pp. 41-44.

[Pina02] C. Pina, "Evolution of the MOSIS VLSI educational program," Proc. Electronic Design, Test, and Applications Workshop, 2002, pp. 187-191.

[Plass07] D. Plass and Y. Chan, "IBM POWER6 SRAM arrays," IBM J. Research and Dev., vol. 51, no. 6, Nov. 2007, pp. 747-756.

[Pollack99] F. Pollack, "New microarchitectural challenges in the coming generations of CMOS process technologies," Intl. Symp. Microarchitecture, Keynote address, 1999.

[Pretorius86] J. Pretorius, A. Shubat, and A. Salama, "Latched domino CMOS logic," JSSC, vol. SC-21, no. 4, Aug. 1986, pp. 514-522.

[Price95] D. Price, "Pentium FDIV flaw-lessons learned," IEEE Micro, vol. 15, no. 2, Apr. 1995, pp. 86-88.

[Proakis08] J. Proakis and M. Salehi, Digital Communications, New York: McGraw Hill, 2008.

[Proebsting91] R. Proebsting, "Speed enhancement technique for CMOS circuits," US Patent 4,985,643, 1991.

[Quach92] N. Quach and M. Flynn, "High-speed addition in CMOS," IEEE Trans. Computers, vol. 41, no. 12, Dec. 1992, pp. 1612-1615.

[Quader94] K. Quader, E. Minami, W. Huang, P. Ko, and C. Hu, "Hot-carrier-reliability design guidelines for CMOS logic circuits," JSSC, vol. 29, no. 3, Mar. 1994, pp. 253-262.

[Ramadass10] Y. Ramadass and A. Chandrakasan, "An efficient piezoelectric energy harvesting interface circuit using a bias-flip rectifier and shared inductor," JSSC, vol. 45, no. 1, Jan. 2010, pp. 189-204.

[Rao03] R. Rao, A. Srivastava, D. Blaauw, and D. Sylvester, "Statistical estimation of leakage current considering inter- and intra-die process variation," Proc. Intl. Symp. Low Power Electronics & Design, Aug. 2003, pp. 84-89.

[Rao07] R. R. Rao, K. Chopra, D. Blaauw, and D. Sylvester, "Computing the soft error rate of a combinational logic circuit using parameterized descriptors," IEEE Trans. CAD, vol. 26, no. 3, Mar. 2007, pp. 468-479.

[Raychowdhury07] A. Raychowdhury and K. Roy, "Carbon nanotube electronics: design of high-performance and low-power digital circuits," IEEE Trans. Circuits & Systems, vol. 54, no. 11, Nov. 2007, pp. 2391-2401.

[Razavi03] B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw Hill, 2003.

[Reddy02] V. Reddy et al., "Impact of negative bias temperature instability on digital circuit reliability," Proc. 40th IEEE Intl. Reliability Physics Symp., 2002, pp. 248-254.

[Restle01] P. Restle et al., "A clock distribution network for microprocessors," JSSC, vol. 36, no. 5, May 2001, pp. 792-799.

[Restle98] P. Restle and A. Deutsch, "Designing the best clock distribution network," Symp. VLSI Circuits Digest Tech. Papers, 1998, pp. 2-5.

[Riordan97] M. Riordan and L. Hoddeson, Crystal Fire: The Invention of the Transistor and the Birth of the Information Age, New York: W. W. Norton & Co, 1998.

[Rizzolo07] R. Rizzolo, "IBM System z9 eFUSE applications and methodology," IBM J. Research and Dev., vol. 51, no. 1/2, Jan./Mar. 2007, pp. 65-75.

[Rohrer05] N. Rohrer et al., "A 64-bit microprocessor in 130-nm and 90-nm technologies with power management features," JSSC, vol. 40, no. 1, Jan. 2005, pp. 19-27.

[Rotella02] F. Rotella, V. Blaschke, and D. Howard, "A broad-band scalable lumped-element inductor model using analytic expressions to incorporate skin effect, substrate loss, and proximity effect," Tech. Digest Intl. Electron Devices Meeting, Dec. 2002, pp. 471-474.

[Roy03] K. Roy, S. Mukhopadhyay, and H. Mahmoodi-Meimand, "Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits," Proceedings of the IEEE, vol. 91, no. 2, Feb. 2003, pp. 305-327.

[Ruehli73] A. Ruehli and P. Brennan, "Efficient capacitance calculations for three-dimensional multiconductor systems," IEEE Trans. Microwave Theory and Techniques, vol. MTT-21, no. 2, Feb. 1973, pp. 76-82.

[Rusu00] S. Rusu and G. Singer, "The first IA-64 microprocessor," JSSC, vol. 35, no. 11, Nov. 2000, pp. 1539-1544.

[Rusu03] S. Rusu, J. Stinson, S. Tam, J. Leung, H. Muljono, and B. Cherkauer, "A 1.5-GHz 130-nm Itanium 2 processor with 6-MB on-die L3 cache," JSSC, vol. 38, no. 11, Nov. 2003, pp. 1887-1895.

[Rusu07] S. Rusu et al., "A 65-nm dual-core multithreaded Xeon processor with 16-MB L3 cache," JSSC, vol. 42, no. 1, Jan. 2007, pp. 17-25.

[Rusu10] S. Rusu et al., "A 45 nm 8-core Enterprise Xeon Processor," JSSC, vol. 45, no. 1, Jan. 2010, pp. 7-14.

[Rzepka98] S. Rzepka, K. Banerjee, E. Meusel, and C. Hu, "Characterization of self-heating in advanced VLSI interconnect lines based on thermal finite element simulation," IEEE Trans. Components, Packaging, and Manufacturing Technology-Part A, vol. 21, no. 3, Sep. 1998, pp. 406-411.

[Sah64] C. Sah, "Characteristics of the Metal-Oxide-Semiconductor Transistors," IEEE Trans. Electron Devices, ED-11, Jul. 1964, pp. 324-345.

[Saint02] C. Saint and J. Saint, IC Mask Design: Essential Layout Techniques, New York: McGraw-Hill, 2002.

[Sakran07] N. Sakran, M. Yuffe, M. Mehalel, J. Doweck, E. Knoll, and A. Kovacs, "The implementation of the 65nm dual-core 64b Merom processor," Proc. Intl. Solid-State Circuits Conf., Feb. 2007, pp. 106-107, 590.

[Sakurai83] T. Sakurai, "Approximation of wiring delay in MOSFET LSI," JSSC, vol. SC-18, no. 4, Aug. 1983, pp. 418-426.

[Sakurai86] T. Sakurai, K. Nogami, M. Kakumu, and T. Iizuka, "Hot-carrier generation in submicrometer VLSI environment," JSSC, vol. SC-21, no. 1, Feb. 1986, pp. 187-192.

[Sakurai90] T. Sakurai and R. Newton, "Alpha-Power Law MOSFET Model and its Applications to CMOS Inverter Delay and Other Formulas," JSSC, vol. 25, no. 2, April 1990, pp. 584-594.

[Sakurai91] T. Sakurai and A. Newton, "Delay analysis of series-connected MOSFET circuits," JSSC, vol. 26, no. 2, Feb. 1991, pp. 122-131.

[Salib04] M. Salib et al., "Silicon photonics," Intel Technology Journal, vol. 08, no. 2, May 2004, pp. 143-160.

[Samson08] G. Samson, N. Ananthapadmanabhan, S. Badrudduza, and L. Clark, "Low-power dynamic memory word line decoding for static random access memories," JSSC, vol. 43, no. 11, Nov. 2008, pp. 2524-2532.

[Samson09] G. Samson and L. Clark, "Low-power race-free programmable logic arrays," JSSC, vol. 44, no. 3, Mar. 2009, pp. 935-946.

[Santoro89] M. Santoro, "Design and Clocking of VLSI Multipliers," Ph.D. thesis, Stanford University, CSL-TR-89-397, 1989.

[Sathe07] V. Sathe, J. Chueh, and M. Papaefthymiou, "Energy-efficient GHz-class charge-recovery logic," JSSC, vol. 42, no. 1, Jan. 2007, pp. 38-47.

[Schellenberg98] F. Schellenberg, H. Zhang, and J. Morrow, "SEMATECH J111 Project: OPC validation," Proc. Optical Microlithography XI, SPIE vol. 3334, 1998, pp. 892-911.

[Schellenberg03] F. Schellenberg, "A little light magic," IEEE Spectrum, vol. 40, no. 9, Sep. 2003, pp. 34-39.

[Schmitt38] O. Schmitt, "A thermionic trigger," J. Scientific Instruments, vol. 15, Jan. 1938, pp. 24-26.

[Schulmann98] W. Schulmann, F. Thimm, and H. Kaiser, "Rotating head for crystal pulling systems for carrying out the Czochralski process," US Patent 5766348, 1998http://download.intel.com/technology/itj/q12001/pdf/art_1.pdf.

[Schultz90] K. Schultz, R. Francis, and K. Smith, "Ganged CMOS: trading standby power for speed," JSSC, vol. SC-25, no. 3, Jun. 1990, pp. 870-873.

[Schutten03] R. Schutten, T. Fitzpatrick, "Design for verification-blueprint for productivity and product quality," Synopsys white paper, 2003.

[Schutz98] J. Schutz and R. Wallace, "A 450 MHz IA32 P6 family microprocessor," Proc. Intl. Solid-State Circuits Conf., Feb. 1998, pp. 236-237.

[Seeds67] R. Seeds, "Yield and cost analysis of bipolar LSI," Intl. Electron Device Meeting, Oct. 1967.

[Seevinck87] E. Seevinck, F. List, and J. Lohstroh, "Static-noise margin analysis of MOS SRAM cells," JSSC, vol. 22, no. 5, Oct. 1987, pp. 748-754.

[Segura04] J. Segura and C. Hawkins, CMOS Electronics: How it Works, How it Fails, Hoboken, NJ: John Wiley & Sons (IEEE Press), 2004.

[Shahidi02] G. Shahidi, "SOI technology for the GHz era," IBM J. Research and Development, vol. 46, no. 2/3, Mar./May 2002, pp. 121-131.

[Sharifkhani09] M. Sharifkhani and M. Sachdev, "SRAM cell stability: a dynamic perspective," JSSC, vol. 44, no. 2, Feb. 2009, pp. 609-619.

[She02] M. She et al., "JVD silicon nitride as tunnel dielectric in p-channel flash memory," IEEE Electron Device Letters, vol. 23, no. 2, Feb. 2002, pp. 91-93.

[Shepard99] K. Shepard, V. Narayanan, and R. Rose, "Harmony: static noise analysis of deep submicron digital integrated circuits," IEEE Trans. Computer-Aided Design, vol. 18, no. 8, Aug. 1999, pp. 1132-1150.

[Sheu87] B. Sheu, D. Scharfetter, P. Ko, and M. Jeng, "BSIM: Berkeley short-channel IGFET model for MOS transistors," JSSC, vol. SC-22, no. 4, Aug. 1987, pp. 558-566.

[Shichman68] H. Shichman and D. Hodges, "Modeling and simulation of insulated-gate field-effect transistor switching circuits," JSSC, vol. SC-3, no. 3, Sep. 1968, pp. 285-289.

[Shigematsu97] S. Shigematsu, S. Mutoh, Y. Matsuya, Y. Tanabe, and J. Yamada, "A 1-V high-speed MTCMOS circuit scheme for power-down application circuits," JSSC, vol. 32, no. 6, Jun. 1997, pp. 861-869.

[Shin05] J. Shin, B. Petrick, M. Singh, and A. Leon, "Design and implementation of an embedded 512-KB level-2 cache subsystem," JSSC, vol. 40, no. 9, Sep. 2005, pp. 1815-1820.

[Shockley52] W. Shockley, "A unipolar 'field-effect' transistor," Proc. IRE, vol. 40, 1952, pp. 1365-1376.

[Shoji82] M. Shoji, "Electrical design of BELLMAC-32a microprocessor," Proc. IEEE Intl. Conf. Circuits and Computers, Sep. 1982, pp. 112-115.

[Shoji86] M. Shoji, "Elimination of process-dependent clock skew in CMOS VLSI," JSSC, vol. SC-21, no. 5, Oct. 1986, pp. 875-880.

[SIA97] Semiconductor Industry Association, International Technology Roadmap for Semiconductors, 1997.

[SIA07] Semiconductor Industry Association, International Technology Roadmap for Semiconductors, 2007.

[Silberman98] J. Silberman et al., "A 1.0-GHz single-issue 64-bit PowerPC integer microprocessor," JSSC, vol. 33, no. 11, Nov. 1998, pp. 1600-1608.

[Singh08] P. Singh, J. Seo, D. Blaauw, and D. Sylvester, "Self-timed regenerators for high-speed and low-power on-chip global interconnect," IEEE Trans. VLSI, vol. 16, no. 6, Jun. 2008, pp. 673-677.

[Sklansky60] J. Sklansky "Conditional-sum addition logic," IRE Trans. Electronic Computers, vol. EC-9, Jun. 1960, pp. 226-231.

[Sklar01] B. Sklar, Digital Communications: Fundamentals and Applications, 2nd ed., Upper Saddle River, NJ: Prentice Hall, 2001.

[Sleight01] J. Sleight et al., "A high performance 0.13 mm SOI CMOS technology with a 70 nm silicon film and with a second generation low-k Cu BEOL," Proc. Intl. Electron Devices Meeting, 2001, pp. 11.3.1-11.3.4.

[Smith99] L. Smith, R. Anderson, D. Forehand, T. Pelc, and T. Roy, "Power distribution system design methodology and capacitor selection for modern CMOS technology," IEEE Trans. Advanced Packaging, vol. 22, no. 3, Aug. 1999, pp. 284-291.

[Sodini84] C. Sodini, Ping-Keung Ko, and J. Moll, "The effect of high fields on MOS device and circuit performance," IEEE Trans. Electron Devices, vol. 31, no. 10, Oct. 1984, pp. 1386-1393.

[Solomatnikov00] A. Solomatnikov, D. Somasekhar, K. Roy, and C. Koh, "Skewed CMOS: noise-immune high-performance low-power static circuit family," Proc. IEEE Intl. Conf. Computer Design, 2000, pp. 241-246.

[Somasekhar96] D. Somasekhar and K. Roy, "Differential current switch logic: a low power DCVS logic family," JSSC, vol. 31, no. 7, Jul. 1996, pp. 981-991.

[Somasekhar98] D. Somasekhar and K. Roy, "LVDCSL: a high fan-in, high-performance, low-voltage differential current switch logic family," IEEE Trans. VLSI, vol. 6, no. 4, Dec. 1998, pp. 573-577.

[Somasekhar00] D. Somasekhar, S. Choi, K. Roy, Y. Ye, and V. De, "Dynamic noise analysis in precharge-evaluate circuits," Proc. Design Automation Conf., 2000, pp. 243-246.

[Song96] M. Song, G. Kang, S. Kim, and B. Kang, "Design methodology for high speed and low power digital circuits with energy economized pass-transistor logic (EEPL)," Proc. 22nd European Solid-State Circuits Conf., 1996, pp. 120-123.

[Song01] S. Song et al., "On the gate oxide scaling of high performance CMOS transistors," Proc. Intl. Electron Devices Meeting, 2001, pp. 3.2.1-3.2.4.

[Sparso01] J. Sparso and S. Furber, eds., Principles of Asynchronous Circuit Design: A Systems Perspective, Boston: Kluwer Academic Publishers, 2001.

[Srinivas92] H. Srinivas and K. Parhi, "A fast VLSI adder architecture," JSSC, vol. 27, no. 5, May 1992, pp. 761-767.

[Srinivasan02] V. Srinivasan et al., "Optimizing pipelines for power and performance," Proc. Intl. Symp. Microarchitecture, 2002, pp. 333-344.

[Stackhouse09] B. Stackhouse et al., "A 65 nm 2-billion transistor quad-core Itanium processor," JSSC, vol. 44, no. 1, Jan. 2009, pp. 18-31.

[Stan98] M. Stan, A. Tenca, and M. Ercegovac, "Long and fast up/down counters," IEEE Trans. Computers, vol. 47, no. 7, Jul. 1998, pp. 722-735.

[Stan99] M. Stan, "Optimal voltages and sizing for low power [CMOS VLSI] ," Proc. Intl. Conf. VLSI Design, Jan. 1999, pp. 428-433.

[Stelling98] P. Stelling, C. Martel, V. Oklobdzija, and R. Ravi, "Optimal circuits for parallel multipliers," IEEE Trans. Computers, vol. 47, no. 3, Mar. 1998, pp. 273-285.

[Stinson03] J. Stinson and S. Rusu, "A 1.5 GHz third generation Itanium processor," Proc. Design Automation Conf., 2003, pp. 706-709.

[Stojanovic99] V. Stojanovic and V. Oklobdzija, "Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems," JSSC, vol. 34, no. 4, Apr. 1999, pp. 536-548.

[Stolk98] P. Stolk, F. Widdershoven, and D. Klaassen, "Modeling statistical dopant fluctuations in MOS transistors," IEEE Trans. Electron Devices, vol. 45, no. 9, Sep. 1998, pp. 1960-1971.

[Stolt08] B. Stolt et al., "Design and Implementation of the POWER6 microprocessor," JSSC, vol. 43, no. 1, Jan. 2008, pp. 21-28.

[Strollo05] A. Strollo, D. De Caro, E. Napoli, and N. Petra, "A novel high-speed sense-amplifier-based flip-flop," IEEE Trans. VLSI, vol. 13, no. 11, Nov. 2005, pp. 1266-1274.

[Stroud02] C. Stroud, A Designer's Guide to Built-in Self-Test, Boston: Kluwer Academic Publishers, 2002.

[Su03] H. Su, F. Liu, A. Devgan, E. Acar, and S. Nassif, "Full chip leakage-estimation considering power supply and temperature variations," Proc. Intl. Symp. Low Power Electronics & Design, Aug. 2003, pp. 78-83.

[Su08] Y. Su, J. Holleman, and B. Otis, "A digital 1.6 pJ/bit chip identification circuit using process variations," JSSC, vol. 43, no. 1, Jan. 2008, pp. 69-77.

[Sun87] J. Sun, Y. Taur, R. Dennard, and S. Klepner, "Submicrometer-channel CMOS for low-temperature operation," IEEE Trans. Electron Devices, vol. ED-34, no. 1, Jan. 1987, pp. 19-26.

[Sutherland99] I. Sutherland, B. Sproull, and D. Harris, Logical Effort: Designing Fast CMOS Circuits, San Francisco, CA: Morgan Kaufmann, 1999.

[Suzuki73] Y. Suzuki, K. Odagawa and T. Abe, "Clocked CMOS calculator circuitry," JSSC, vol. SC-8, no. 6, Dec. 1973, pp. 462-469.

[Suzuki93] M. Suzuki, N. Ohkubo, T. Shinbo, T. Yamanaka, A. Shimizu, K. Sasaki, and Y. Nakagome, "A 1.5-ns 32-b CMOS ALU in double pass-transistor logic," JSSC, vol. 28, no. 11, Nov. 1993, pp. 1145-1151.

[Svensson03] C. Svensson, "Forty years of feature-size predictions (1962-2002)," Proc. Intl. Solid-State Circuits Conf., 2003, pp. 35-36.

[Swanson72] R. Swanson and J. Meindl, "Ion-implanted complementary MOS transistors in low-voltage circuits," JSSC, vol. 7, no. 2, Apr. 1972, pp. 146-153.

[Sweeney02] P. Sweeney, Error Control Coding: From Theory to Practice, New York: John Wiley & Sons, 2002.

[Sylvester98] D. Sylvester and K. Keutzer, "Getting to the bottom of deep submicron," Proc. IEEE/ACM Intl. Conf. Computer-Aided Design, 1998, pp. 203-211.

[Takahashi98] M. Takahashi et al., "A 60-mW MPEG4 video codec using clustered voltage scaling with variable supply-voltage scheme," JSSC, vol. 33, no. 11, Nov. 1998, pp. 1772-1780.

[Takeuchi94] K. Takeuchi and M. Fukuma, "Effects of the velocity saturated region on MOSFET characteristics," IEEE Trans. Electron Devices, vol. 41, no. 9, Sep. 1994, pp. 1623-1627.

[Tam00] S. Tam, S. Rusu, U. Desai, R. Kim, J. Zhang, and I. Young, "Clock generation and distribution for the first IA-64 microprocessor," JSSC, vol. 35, no. 11, Nov. 2000, pp. 1545-1552.

[Tam04] S. Tam, R. Limaye, and U. Desai, "Clock generation and distribution for the 130-nm Itanium 2 processor with 6-MB on-die L3 cache," JSSC, vol. 39, no. 4, Apr. 2004.

[Tang97] X. Tang, V. De, and J. Meindl, "Intrinsic MOSFET parameter fluctuations due to random dopant placement," IEEE Trans. VLSI, vol. 5, no. 4, Dec 1997, pp. 369-376.

[Tawfik09] S. Tawfik and V. Kursun, "Low power and high speed multi threshold voltage interface circuits," IEEE Trans. VLSI, vol. 17, no. 5, May 2009, pp. 638-645.

[Tharakan92] G. Tharakan and S. Kang, "A new design of a fast barrel switch network," JSSC, vol. 27, no. 2, Feb. 1992, pp. 217-221.

[Thompson02] S. Thompson et al., "A 90 nm logic technology featuring 50 nm strained silicon channel transistors, 7 layers of Cu interconnects, low k ILD, and 1 mm² SRAM cell," Proc. Intl. Electron Devices Meeting, 2002, pp. 61-64.

[Thompson04] S. Thompson et al., "A logic nanotechnology featuring strained-silicon," IEEE Electron Device Letters, vol. 25, no. 4, Apr. 2004, pp. 191-193.

[Thorp99] T. Thorp, G. Yee, and C. Sechen, "Design and synthesis of monotonic circuits," Proc. IEEE Intl. Conf. Computer Design, 1999, pp. 569-572.

[Tierno08] J. Tierno, A. Rylyakov, and D. Friedman, "A wide power supply range, wide tuning range, all static CMOS all digital PLL in 65 nm SOI," JSSC, vol. 43, no. 1, Jan. 2008, pp. 42-51.

[Tobias95] P. Tobias and D. Trindade, Applied Reliability, 2nd ed., New York: Van Nostrand Reinhold, 1995.

[Toh88] K. Toh, P. Ko, and R. Meyer, "An engineering model for short-channel MOS devices," JSSC, vol. 23, no. 4, Aug. 1988, pp. 950-958.

[Tokunaga08] C. Tokunaga, D. Blaauw, and T. Mudge, "True random number generator with a metastability-based quality control," JSSC, vol. 43, no. 1, Jan. 2008, pp. 78-85.

[Topaloglu07] R. Topaloglu, "Standard cell and custom circuit optimization using dummy diffusions through STI width stress effect utilization," Proc. Custom Integrated Circuits Conf., Sep. 2007, pp. 619-622.

[Topol06] A. Topol et al., "Three-dimensional integrated circuits," IBM J. Research and Dev., vol. 50, no. 4/5, Jul./Sep. 2006, pp. 491-506.

[Trinh09] C. Trinh et al., "A 5.6MB/s 64Gb 4b/cell NAND flash memory in 43nm CMOS," Proc. Intl. Solid-State Circuits Conf., Feb. 2009, pp. 246-247, 247a.

[Troutman86] R. Troutman, Latchup in CMOS Technology: The Problem and its Cure, Boston: Kluwer Academic Publishers, 1986.

[Tschanz01] J. Tschanz, S. Narendra, Zhanping Chen, S. Borkar, M. Sachdev, and Vivek De, "Comparative delay and energy of single edge-triggered and dual edge-triggered pulsed flip-flops for high-performance microprocessors," Proc. Intl. Symp. Low Power Electronics & Design, 2001, pp. 147-152.

[Tschanz02] J. Tschanz et al., "Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage," JSSC, vol. 37, no. 11, Nov. 2002, pp. 1396-1402.

[Tschanz03] J. Tschanz, S. Narendra, Y. Ye, B. Bloechel, S. Borkar, and V. De, "Dynamic sleep transistor and body bias for active leakage power control of microprocessors," JSSC, vol. 38, no. 11, Nov. 2003, pp. 1838-1845.

[Tschanz03b] J. Tschanz, S. Narendra, R. Nair, and V. De, "Effectiveness of adaptive supply voltage and body bias for reducing impact of parameter variations in low power and high performance microprocessors," JSSC, vol. 38, no. 5, May 2003, pp. 826-829.

[Tschanz07] J. Tschanz et al., "Adaptive frequency and biasing techniques for tolerance to dynamic temperature-voltage variations and aging," Proc. Intl. Solid-State Circuits Conf., Feb. 2007, pp. 292-604.

[Tsividis99] Y. Tsividis, Operation and Modeling of the MOS Transistor, 2nd ed., Boston: McGraw-Hill, 1999.

[Tyagi93] A. Tyagi, "A reduced-area scheme for carry-select adders," JSSC, vol. 42, no. 10, Oct. 1993, pp. 1163-1170.

[Tyagi00] S. Tyagi et al., "A 130 nm generation logic technology featuring 70 nm transistors, dual V_t transistors and 6 layers of Cu interconnects," Proc. Intl. Electron Devices Meeting, 2000, pp. 567-570.

[Tyagi05] S. Tyagi et al., "An advanced low power, high performance, strained channel 65nm technology," Proc. Intl. Electron Devices Meeting, Dec. 2005, pp. 245-247.

[Uehara81] T. Uehara and W. van Cleemput, "Optimal layout of CMOS functional arrays," IEEE Trans. Computers, vol. C-30, no. 5, May 1981, pp. 305-312.

[Unger86] S. Unger and C. Tan, "Clocking schemes for high-speed digital systems," IEEE Trans. Computers, vol. 35, no. 10, Oct. 1986, pp. 880-895.

[Usami95] K. Usami and M. Horowitz, "Clustered voltage scaling for low-power design," Proc. Intl. Symp. Low Power Electronics and Design, 1995, pp. 3-8.

[Vadasz66] L. Vadasz and A. Grove, "Temperature dependence of MOS transistor characteristics below saturation," IEEE. Trans. Electron Devices, vol. ED-13, no. 13, 1966, pp. 863-866.

[Vadasz69] L. Vadasz, A. Grove, T. Rowe, and G. Moore, "Silicon-gate technology," IEEE Spectrum, vol. 6, no. 10, Oct. 1969, pp. 28-35.

[van Berkel99] C. van Berkel and C. Molnar, "Beware the three-way arbiter," JSSC, vol. 34, no. 6, Jun. 1999, pp. 840-848.

[Vangal02] S. Vangal et al., "5-GHz 32-bit integer execution core in 130-nm dual-V_T CMOS," JSSC, vol. 37, no. 11, Nov. 2002, pp. 1421-1432.

[Veendrick80] H. Veendrick, "The behavior of flip-flops used as synchronizers and prediction of their failure rate," JSSC, vol. SC-15, no. 2, Apr. 1980, pp. 169-176.

[Veendrick84] H. Veendrick, "Short-circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits," JSSC, vol. SC-19, no. 4, Aug. 1984, pp. 468-473.

[Vittal99] A. Vittal et al., "Crosstalk in VLSI interconnections," IEEE Trans. Computer-Aided Design, vol. 18, no. 12, Dec. 1999, pp. 1817-1824.

[Vittoz72] E. Vittoz, B. Gerber, and F. Leuenberger, "Silicon-gate CMOS frequency divider for electronic wrist watch," JSSC, vol. 7, no. 2, Apr. 1972, pp. 100-104.

[Volk01] A. Volk, P. Stoll, and P. Metrovich, "Recollections of early chip development at Intel," Intel Technology Journal, Q1 2001, pp. 1-12.

[Vollertsen99] R. Vollertsen, "Burn-in," IEEE Integrated Reliability Workshop Final Report, 1999, pp. 167-173.

[von Arnim05] K. von Armin, et al., "Efficiency of body biasing in 90-nm CMOS for low-power digital circuits," JSSC, vol. 40, no. 7, July 2005, pp. 1549-1556.

[von Neumann51] J. von Neumann, "Various techniques used in connection with random digits," notes by Forsythe, G., National Bureau of Standards Applied Math Series, 1951, vol. 12, pp. 36-38. Reprinted in von Neumann's Collected Works, vol. 5, Pergamon Press, 1963, pp. 768-770.

[von Neumann66] J. von Neumann, Theory of Self-Reproducing Automata, Urbana, IL: Univ. Illinois Press, 1966.

[Wadell01] B. Wadell, Transmission Line Design Handbook, Norwood, MA: Artech House, 1991.

[Wakerly00] J. Wakerly, Digital Design Principles and Practices, 3rd ed., Upper Saddle River, NJ: Prentice Hall, 2000.

[Wallace64] C. Wallace, "A suggestion for a fast multiplier," IEEE Trans. Electronic Computers, Feb. 1964, pp. 14-17.

[Wang86] L. Wang and E. McCluskey, "Complete feedback shift register design for built-in self test," Proc. Design Automation Conf., Nov. 1986, pp. 56-59.

[Wang89] J. Wang, C. Wu, and M. Tsai, "CMOS nonthreshold logic (NTL) and cascode nonthreshold logic (CNTL) for high-speed applications," JSSC, vol. 24, no. 3, Jun. 1989, pp. 779-786.

[Wang93] Z. Wang, G. Jullien, W. Miller, and J. Wang, "New concepts for the design of carry-lookahead adders," Proc. IEEE Intl. Symp. Circuits and Systems, vol. 3, 1993, pp. 1837-1840.

[Wang94] J. Wang, S. Fang, and W. Feng, "New efficient designs for XOR and XNOR functions on the transistor level," JSSC, vol. 29, no. 7, Jul. 1994, pp. 780-786.

[Wang97] Z. Wang, G. Jullien, W. Miller, J. Wang, and S. Bizzan, "Fast adders using enhanced multiple-output domino logic," JSSC, vol. 32, no. 2, Feb. 1997, pp. 206-214.

[Wang00] J. Wang and C. Huang, "High-speed and low-power CMOS priority encoders," JSSC, vol. 35, no. 10, Oct. 2000, pp. 1511-1514.

[Wang01] J. Wang, C. Chang, and C. Yeh, "Analysis and design of high-speed and low-power CMOS PLAs," JSSC, vol. 36, no. 8, Aug. 2001, pp. 1250-1262.

[Wang02] A. Wang, A. Chandrakasan, and S. Kosonocky, "Optimal supply and threshold scaling for subthreshold CMOS circuits," Proc. Computer Society Symp. VLSI, 2002, pp. 5-9.

[Wang06] G. Wang et al., "A 0.127 mm² high performance 65 nm SOI based embedded DRAM for on-processor applications," Proc. Intl. Electron Devices Meeting, Dec. 2006, pp. 1-4.

[Wang07] C. Wang, C. Lee, and W. Lin, "A 4-kb low-power SRAM design with negative word-line scheme," IEEE Trans. Circuits & Systems, vol. 54, no. 5, May 2007, pp. 1069-1076.

[Wang08a] A. Wang and S. Naffziger, eds., Adaptive Techniques for Dynamic Processor Optimization: Theory and Practice, New York: Springer, 2008.

[Wang08b] L. Wang, C. Stroud, and N. Touba, eds., System-on-Chip Test Architectures: Nanometer Design for Testability, Elsevier, 2008.

[Wanlass63] F. Wanlass and C. Sah, "Nanowatt logic using field effect metal-oxide semiconductor triodes," Proc. IEEE Intl. Solid-State Circuits Conf., 1963, pp. 32-33.

[Warnock06] J. Warnock et al., "Circuit design techniques for a first-generation cell broadband engine processor," JSSC, vol. 41, no. 8, Aug. 2006, pp. 1692-1706.

[Webb97] C. Webb et al., "A 400-MHz S/390 microprocessor," JSSC, vol. 32, no. 11, Nov. 1997, pp. 1665-1675.

[Webb08] C. Webb, "45 nm design for manufacturing," Intel Technology Journal, vol. 12, no. 2, Jun. 2008, pp. 121-130.

[Wei98] L. Wei, Z. Chen, M. Johnson, K. Roy, and V. De, "Design and optimization of low voltage high performance dual threshold CMOS circuits," Proc. Design Automation Conf., 1998, pp. 489-494.

[Wei00] G. Wei, J. Kim, D. Liu, S. Sidiropoulos, and M. Horowitz, "A variable-frequency parallel I/O interface with adaptive power-supply regulation," JSSC, vol. 35, no. 11, Nov. 2000, pp. 1600-1610.

[Weinberger58] A. Weinberger and J. Smith, "A logic for high-speed addition," System Design of Digital Computer at the National Bureau of Standards: Methods for High-Speed Addition and Multiplication, National Bureau of Standards, circular 591, section 1, Feb. 1958, pp. 3-12.

[Weinberger81] A. Weinberger, "4-2 carry-save adder module," IBM Technical Disclosure Bulletin, vol. 23, no. 8, Jan. 1981, pp. 3811-3814.

[Weinlader00] D. Weinlader, Ron Ho, Chih-Kong Keng Yang, and M. Horowitz, "An eight channel 35 GSample/s CMOS timing analyzer," Proc. Intl. Solid-State Circuits Conf., 2000, pp. 170-171.

[Weiss02] D. Weiss, J. Wuu, and V. Chin, "The on-chip 3-MB subarray-based third-level cache on an Itanium microprocessor," JSSC, vol. 37, no. 11, Nov. 2002, pp. 1523-1529.

[Widmer83] A. Widmer and P. Franaszek, "A DC-balanced partitioned-block 8B/10B transmission code," IBM J. Research and Dev., vol. 27, no. 5, Sep. 1983, pp. 440-451.

[Wijeratne07] S. Wijeratne et al., "A 9-GHz 65-nm Intel Pentium 4 processor integer execution unit," JSSC, vol. 42, no. 1, Jan. 2007, pp. 26-37.

[Williams83] T. Williams and K. Parker, "Design for Testability-A Survey," Proc. IEEE, vol. 71, no. 1, Jan. 1983, pp. 98-112.

[Williams86] T. Williams, "Design for testability," Proc. NATO Advanced Study Inst. Computer Design Aids for VLSI Circuits, (P. Antognetti et al., eds.), NATO ASI Series, Martinus Nijhoff Publishers, 1986, pp. 359-416.

[Williams91] T. Williams and M. Horowitz, "A zero-overhead self-timed 160-ns 54-b CMOS divider," JSSC, vol. 26, no. 11, Nov. 1991, pp. 1651-1661.

[Wilton96] S. Wilton and N. Jouppi, "CACTI: an enhanced cache access and cycle time model," JSSC, vol. 31, no. 5, May 1996, pp. 677-688.

[Wing82] O. Wing, "Automated gate matrix layout," Proc. IEEE Intl. Symp. Circuits and Systems, vol. 2, 1982, pp. 681-685.

[Wolf00] S. Wolf and R. Tauber, Silicon Processing for the VLSI Era, 2nd ed., Sunset Beach, CA: Lattice Press, 2000.

[Wong03] H. Wong, J. Appenzeller, V. Derycke, R. Martel, S. Wind, and P. Avouris, "Carbon nanotube field effect transistors-fabrication, device physics, and circuit implications," Proc. Intl. Solid-State Circuits Conf., 2003, pp. 370-500.

[Wong06] K. Wong, T. Rahal-Arabi, M. Ma, and G. Taylor, "Enhancing microprocessor immunity to power supply noise with clock-data compensation," JSSC, vol. 41, no. 4, Apr. 2006, pp. 749-758.

[Wu91] C. Wu and K. Cheng, "Latched CMOS differential logic (LCDL) for complex high-speed VLSI," JSSC, vol. 26, no. 9, Sep. 1991, pp. 1324-1328.

[Xu08] J. Xu et al., "A band-limited active damping circuit with 13 dB power supply resonance reduction," JSSC, vol. 43, no. 1, Jan. 2008, pp. 61-68.

[Yabuuchi07] M. Yabuuchi et al., "A 45nm low-standby-power embedded SRAM with improved immunity against process and temperature variations," Proc. Intl. Solid-State Circuits Conf., Feb. 2007, pp. 326-606.

[Yamada95] H. Yamada, T. Hotta, T. Nishiyama, F. Murabayashi, T. Yamauchi, and H. Sawamoto, "A 13.3 ns double-precision floating-point ALU and multiplier," Proc. Intl. Conf. Computer Design, 1995, pp. 466-470.

[Yamaoka04] M. Yamaoka, K. Osada, and K. Ishibashi, "0.4-V logic-library-friendly SRAM array using rectangular-diffusion cell and delta-boosted-array voltage scheme," JSSC, vol. 39, no. 6, Jun. 2004, pp. 934-940.

[Yamaoka04b] M. Yamaoka et al., "A 300MHz 25 mA/Mb leakage on-chip SRAM module featuring process-variation immunity and low-leakage-active mode for mobile-phone application processor," Proc. Intl. Solid-State Circuits Conf., Feb. 2004, pp. 494-542.

[Yamaoka06] M. Yamaoka et al., "90-nm process-variation adaptive embedded SRAM modules with power-line-floating write technique," JSSC, vol. 41, no. 3, Mar. 2006, pp. 705-711.

[Yang96] C. K. Yang and M. Horowitz, "A 0.8-mm CMOS 2.5 Gb/s oversampling receiver and transmitter for serial links," JSSC, vol. 31, no. 12, Dec. 1996, pp. 2015-2023.

[Yang98] S. Yang et al., "A high performance 180 nm generation logic technology," Tech. Digest Intl. Electron Device Meeting, Dec. 1998, pp. 197-200.

[Yano90] K. Yano, T. Yamanaka, T. Nishida, M. Saito, K. Shimohigashi, and A. Shimizu, "A 3.8-ns 16x16-b multiplier using complementary pass-transistor logic," JSSC, vol. 25, no. 2, Apr. 1990, pp. 388-395.

[Yano96] K. Yano, Y. Sasaki, K. Rikino, and K. Seki, "Top-down pass-transistor logic design," JSSC, vol. 31, no. 6, Jun. 1996, pp. 792-803.

[Ye98] Y. Ye, S. Borkar, and V. De, "A new technique for standby leakage reduction in high-performance circuits," Symp. VLSI Circuits Digest Tech. Papers, 1998, pp. 40-41.

[Ye00] Y. Ye, J. Tschanz, S. Narendra, S. Borkar, M. Stan, and V. De, "Comparative delay, noise and energy of high-performance domino adders with stack node preconditioning (SNP)," Symp. VLSI Circuits Digest Tech. Papers, 2000, pp. 188-191.

[Yee00] G. Yee and C. Sechen, "Clock-delayed domino for dynamic circuit design," IEEE Trans. VLSI, vol. 8, no. 4, Aug. 2000, pp. 425-430.

[Yoon02] J. Yoon et al., "CMOS-compatible surface-micromachined suspended-spiral inductors for multi-GHz silicon RF ICs," IEEE Electron Device Letters, vol. 23, no. 10, Oct. 2002, pp. 591-593.

[Yoshimoto83] M. Yoshimoto et al., "A divided word-line structure in the static RAM and its application to a 64K full CMOS RAM," JSSC, vol. SC-18, no. 5, Oct. 1983, pp. 479-485.

[Young00] K. Young et al., "A 0.13 mm CMOS technology with 193 nm lithography and Cu/Low-k for high performance applications," Proc. Intl. Electron Devices Meeting, 2000, pp. 563-566.

[Young10] I. Young et al., "Optical I/O technology for tera-scale computing," JSSC, vol. 45, no. 1, Jan. 2010, pp. 235-248.

[Yuan82] C. Yuan and T. Trick, "A simple formula for the estimation of the capacitance of two-dimensional interconnects in VLSI circuits," IEEE Electron Device Letters, vol. EDL-3, Dec. 1982, pp. 391-393.

[Yuan89] J. Yuan and C. Svensson, "High-speed CMOS circuit technique," JSSC, vol. 24, no. 1, Feb. 1989, pp. 62-70.

[Zerbe01] J. Zerbe et al., "A 2 Gb/s/pin 4-PAM parallel bus interface with transmit crosstalk cancellation, equalization, and integrating receivers," Proc. Intl. Solid-State Circuits Conf., 2001, pp. 66-67, 432.

[Zhai05a] B. Zhai, D. Blaauw, D. Sylvester, and K. Flautner, "The limit of dynamic voltage scaling and insomniac dynamic voltage scaling," IEEE Trans. VLSI, vol. 13, no. 11, Nov. 2005, pp. 1239-1252.

[Zhai05b] B. Zhai, S. Hanson, D. Blaauw, and D. Sylvester, "Analysis and mitigation of variability in subthreshold design," Proc. Intl. Symp. Low Power Electronics & Design, Aug. 2005, pp. 20-25.

[Zhai08] B. Zhai, S. Hanson, D. Blaauw, and D. Sylvester, "A variation-tolerant sub-200 mV 6-T subthreshold SRAM," JSSC, vol. 43, no. 10, Oct. 2008, pp. 2338-2348.

[Zhang05] K. Zhang et al., "SRAM design on 65-nm CMOS technology with dynamic sleep transistor for leakage reduction," JSSC, vol. 40, no. 4, Apr. 2005, pp. 895-901.

[Zhang06] K. Zhang et al., "A 3-GHz 70-mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply," JSSC, vol. 41, no. 1, Jan. 2006, pp. 146-151.

[Zhao07] P. Zhao, J. McNeely, P. Golconda, M. Bayoumi, R. Barcenas, and Weidong Kuang, "Low-power clock branch sharing double-edge triggered flip-flop," IEEE Trans. VLSI, vol. 15, no. 3, Mar. 2007, pp. 338-345.

[Zhao09] P. Zhao et al., "Low-power clocked-pseudo-NMOS flip-flop for level conversion in dual supply systems," IEEE Trans. VLSI, vol. 17, no. 9, Sep. 2009, pp. 1196-1202.

[Zhou99] X. Zhou, K. Lim, and D. Lim, "A simple and unambiguous definition of threshold voltage and its implications in deep-submicron MOS device modeling," IEEE Trans. Electron Devices, vol. 46, no. 4, Apr. 1999, pp. 807-809.

[Ziegler96] J. Ziegler, "Terrestrial cosmic rays," IBM J. Research and Development, vol. 40, no. 1, Jan. 1996, pp. 19-39.

[Ziegler02] J. Ziegler, Ion-Implantation-Science and Technology, 2002 ed., IIT Press, 2002.

[Zimmermann96] R. Zimmermann, "Non-heuristic optimization and synthesis of parallel-prefix adders," Proc. Intl. Workshop on Logic and Architecture Synthesis, Dec. 1996, pp. 123-132.

[Zimmermann97] R. Zimmermann and W. Fichtner, "Low-power logic styles: CMOS versus pass-transistor logic," JSSC, vol. 32, no. 7, Jul. 1997, pp. 1079-1090.

[Zlatanovici09] R. Zlatanovici, S. Kao, and B. Nikolic, "Energy-delay optimization of 64-bit carry-lookahead adders with a 240 ps 90 nm CMOS design example," JSSC, vol. 44, no. 2, Feb. 2009, pp. 569-583.

[Zuras86] D. Zuras and W. McAllister, "Balanced delay trees and combinatorial division in VLSI," JSSC, vol. SC-21, no. 5, Oct. 1986, pp. 814-819.