E154: System-on-Chip Design

Spring 2025


Administrative
Syllabus
Gradescope
Spring 2023
Spring 2021
References
Digital Design & Computer Architecture
RISC-V Spec
HMC E190AX Slack Channel
Questa Manual
SystemVerilog Standard
Compiler Explorer
RISC-V Online Assembler
Assembler/Disassembler
WebFloat
HDL Bits Verilog Practice
Project
Project Requirements
CORE-V-Wally Repository
gates.vsd Visio template
Textbook (HMC Only)
Instruction Set Summary
Privileged & Other Extensions
Copyedited Manuscript
1: History
2: RISC-V
Labs
Lab 0: Getting Started
Lab 1: Programming
Lab 2: Verification
Lab 3: Debug
Lab 4: Design
Lab 5: Synthesis

Project
Final Project: FMA

Problem Sets
PS Rotation
Draft Exercises

Slides
1 Intro
2 RISC-V
3: HDL
4: Pipelining
5: Verification
6: Synthesis
7: Pipeline
8: Privileged
9: Bus
10: Cache
11: Memory Management Unit
12: Load/Store Unit
13: Instruction Fetch Unit<>/a>
14: Compressed Instructions
15: Multiply/Divide Unit
16: Floating-Point Unit
17: Atomic Instructions
18: Bit Manipulation
19: Other Extensions
20: Peripherals
21: Benchmarking
22: Linux
A: Linux Guide
B: GITting Around