The LXRE SIMD Coprocessor

This LXRE processor can have attached a LXRE SIMD Coprocessor (LSC).

Overview

The standard coprocessor for the LXRE is a 16 word-wide maskable SIMD processor. Like the LXRE processor, the LSC has 32 registers which are memory mapped. In addition, the coprocessor supports masking of results and 16 instructions on a queue at once. The instruction set for LSC is the same as the LXRE R-type instructions (currently the simulator only supports ADD/MUL).

Memory Mapping

The address space 0x1800 - 0x2000 is reserved by LSC. The address space is broken up as follows

15 - 1110 - 65 - 21 - 0
00011 REG IDX 00
REG 0 is reserved for mask and instruction space. REG 0, IDX 0 represents the mask (leave this 0 for now). REG 0, IDX 1-15 are instructions. REG 1-32, IDX 0-15 are the words in registers 1-32.

Sending an Instruction

To send an instruction to the LSC, write the instruction value to one of REG 0, IDX 1-15. When read, each memory location will retain the value of the instruction until the instruction is executed. Then the instruction will be replaced with a 0. For instance to execute an instruction, one might do the following,

LA $T0, INSTR SW $T0, 0x1801 busy_wait: LW $T0, 0x1801 BNEZ $T0, busy_wait