Here is the tentative schedule for the class.

# Monday Wednesday Friday
1 Sep 01
Labor Day
Sep 03
Binary, logic gates, logic levels
1.1-1.5,A.1-A.2,A.5-A.7
Sep 05
2 Sep 08
Transistors; Truth tables; Boolean expressions; Boolean algebra
1.6, 1.7,1.9, 2.1-2.3
Sep 10
K-maps; Xs and Zs; multiplexers and decoders; priority circuit; timing; hazards
2.4-2.10
Sep 12
Lab 1 Due
3 Sep 15
HW 1 Due
sequential circuits: SR latches; D latches, flip-flops, clocking
3.1-3.3.3
Sep 17
finite state machines (FSMs)
3.4
Sep 19
Lab 2 Due
4 Sep 22
HW 2 Due
dynamic discipline, metastability, parallelism
3.5.1-3.5.6,3.6, 3.7
Sep 24
System Verilog 1
4.1-4.4
Sep 26
Lab 3 Due
5 Sep 29
HW 3 Due
System Verilog 2
4.4-4.9
Oct 01
arithmetic: adders, subtractors, comparators, ALUs
5.1-5.2.8
Oct 03
Lab 4 Due
6 Oct 06
HW 4 Due
number systems: fixed & floating
5.3
Oct 08
sequential building blocks: counter, shift register, memory arrays: RAMs, ROMs, logic arrays: PLAs, FPGAs
5.4, 5.5, 5.6, 5.7
Oct 10
Lab 5 Due
7 Oct 13
HW 5 Due
Problems/Review
Oct 15
Problems/Review
Oct 17
Midterm Due
8 Oct 20
Fall Break
Oct 22
C-programming 1
c.1-c.6
Oct 24
9 Oct 27
C-programming 2
c.7-c.1
Oct 29
ARM instruction set and registers
6.1-6.3
Oct 31
10 Nov 03
Lab 6 Due
branches & procedure calls; addressing modes
6.4-6.5
Nov 05
linking & launching applications
6.6-6.7.1
Nov 07
Lab 7 Due
11 Nov 10
HW 7 Due
single-cycle processor data path and control
7.1-7.3.4
Nov 12
single-cycle processor control
7.1-7.3.4
Nov 14
Lab 8 Due
12 Nov 17
multi-cycle processor
7.4.1-7.4.4
Nov 19
HW 8 Due
pipelining hazards and stalls
7.5.1-7.5.5
Nov 21
Lab 9 Due
13 Nov 24
Lab 9 Review
Nov 26
HW 9 Due
advanced microarchitecture
7.7-7.8
Nov 28
Thanksgiving
14 Dec 01
memory system, performance
8.1, 8.2
Dec 03
caches and virtual memory
8.3-8.44
Dec 05
Lab 10 Due
15 Dec 08
memory-mapped, embedded and PC I/O
8.5-8.7
Dec 10
HW 10 Due
Review/Final Distribution
Dec 12
Last Day of Classes
Lab 11 Due
16 Dec 15
Finals Week
Final Due (5 PM)
Dec 17
Finals Week
Dec 19
Finals Week