Digital Design and Computer Architecture: RISC-V Edition
Sarah L. Harris and David Harris
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Chapter 1
0:
Introduction
1:
Managing Complexity/Design Principles
2:
Unsigned Binary Numbers
3:
Hexadecimal Numbers
4:
Bytes, Nibbles & All That Jazz
5:
Binary Addition
6:
Signed Numbers
7:
Extension
8:
Logic Gates
9:
Transistors
10:
Gates from Transistors
11:
Power Consumption of Digital Circuits
Chapter 2
1:
Introduction
2:
Combinational Circuits
3:
Boolean Equations: SOP and POS Forms
4:
Boolean Axioms
5:
Boolean Theorems of One Variable
6:
Boolean Theorems of Multiple Variables
7:
Simplifying Equations & Proving Theorems
8:
From Logic to Gates
9:
Bubble Pushing
10:
X's and Z's
11:
Karnaugh Maps (K-Maps)
12:
K-Maps with Don't Cares
13:
Multiplexers
14:
Decoders
15:
Timing of Combinational Logic
Chapter 3
1:
Introduction
2:
State Element 1: Bistable Circuit
3:
State Element 2: SR Latch
4:
State Element 3: D Latch
5:
State Element 4: D Flip-Flop
6:
Flip-Flop Variations
7:
Synchronous Sequential Logic
8:
Intro to Finite State Machines (FSMs)
9:
Moore FSM Example 1
10:
Moore FSM Example 2
11:
Mealy FSM Example
12:
Factored FSMs
13:
Timing
14:
Clock Skew
15:
Metastability
16:
Synchronizers
17:
Parallelism
Chapter 4
1:
Introduction
2:
Combinational Logic
3:
Delays in Simulation
4:
Sequential Logic
5:
Combinational logic using always
6:
Signal Assignments
7:
Finite State Machines (FSMs)
8:
Parameterized Modules
9:
Testbenches
Chapter 5
1:
Introduction
2:
Adders Introduction
3:
Ripple-Carry Adders
4:
Carry Lookahead Adders (CLAs)
5:
Prefix Adders
6:
Subtractors & Comparators
7:
Arithmetic Logic Units (ALUs)
8:
Shifters, Multipliers & Dividers
9:
Fixed Point Numbers
10:
Floating-Point Numbers
11:
Floating-Point Addition
12:
Counters & Shift Registers
13:
Memory Introduction
14:
RAM
15:
ROM
16:
Memory Arrays in SystemVerilog
17:
Logic Arrays
Chapter 6
1:
Introduction
2:
Instructions
3:
Operands
4:
Memory Instructions
5:
Immediates (Constants)
6:
Logical Instructions
7:
Multiply & Divide Instructions
8:
Branches
9:
Conditional Statements & Loops
10:
Arrays
11:
Functions
12:
The Stack
13:
Recursive Functions
14:
More on Jumps & Pseudoinstructions
15:
Machine Language: R-Type Instruction Formats
16:
Machine Language: I, S/B, U/J-Type Instr. Formats
17:
Immediate Encodings
18:
Decoding Instructions & Addressing Modes
19:
Compiling, Assembling & Loading Programs
20:
Big-Endian & Little-Endian Memory
21:
Signed & Unsigned Instructions
22:
Compressed Instructions
23:
Floating-Point Instructions
Chapter 7
1:
Introduction
2:
Single-Cycle Processor: Datapath lw Instruction
3:
Single-Cycle Processor: Datapath Other Instructions
4:
Single-Cycle Processor: Control
5:
Single-Cycle Processor: Extending
6:
Single-Cycle Processor: Performance
6a:
Single-Cycle Processor: Testbench
6b:
Single-Cycle Processor: SystemVerilog
6c:
Single-Cycle Processor: Tie Celebration
7:
Multicycle Processor: Datapath for lw
8:
Multicycle Processor: Datapath for Other Instr.
9:
Multicycle Processor: Control FSM for lw
10:
Multicycle Processor: Control for Other Instr.
11:
Multicycle Processor: Extending to other Instructions
12:
Multicycle Processor: Performance
13:
Pipelined Processor: Introduction
14:
Pipelined Processor: Data Hazards
15:
Pipelined Processor: Control Hazards
16:
Pipelined Processor: Performance
17:
Advanced Microarchitecture
18:
Superscalar & Out of Order Processors
19:
Multithreading & Multiprocessors
Chapter 8
1:
Introduction
2:
Memory System Performance
3:
Cache Introduction
4:
Direct-Mapped Caches
5:
Associative Caches
6:
Spatial Locality
7:
LRU (Least-Recently Used) Replacement
8:
Cache Summary
9:
Virtual Memory Introduction
10:
Address Translation
11:
Page Tables
12:
TLBs (Translation Lookaside Buffers)
13:
Virtual Memory Summary
Chapter 9
1:
Introduction
2:
RISC-V Microcontrollers
3:
Memory-mapped I/O
4:
General-Purpose I/O (GPIO)
5:
RISC-V Device Driver Library
6:
Timers
7:
Morse Code Example
8:
Interfaces
9:
SPI
10:
SPI Accelerometer Example
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