21164 R10000 High Speed CMOS Circuit Design
Spring 1998 - Harris


Contents

- Course Description
- Handouts
- Online Documentation
- Teaching Staff


Course Description

As the computer industry grows exponentially, demand for skilled circuit designers has consistently outpaced supply. Now that processor designers are aggressively using circuit techniques, striving for a gigahertz and beyond, the field is especially exciting.

This course provides hands-on instruction in high-speed CMOS circuit design. You focus on using hand estimation and SPICE simulation to rapidly and accurately design circuits, choosing the appropriate domino design and advanced synchronous and asynchronous timing methodologies used in high-speed applications, and designing fast ALUs and memories. Weekly assignments build toward the final project of a simple microprocessor execution unit running more than 500 MHZ.

Mastering the topics of this course will transform your circuit design experience from the drudgery of piloting a circuit simulator into the exciting adventure of pushing chips to their utmost limits. Engineers who would like to hone their circuit design skills or who have background in another field of VLSI design and would like to move to circuit design would benefit from this course. Enrollment is limited.

Prerequisites: An introductory class covering CMOS circuit design and an understanding of static CMOS gate design and familiarity with layout. Students are also required to have the ability to access SPICE outside of class.

DAVID HARRIS, M.Eng.E.E, is working on a Ph.D. in high-speed circuit design at Stanford University while investigating asynchronous circuit techniques at Sun Microsystems Laboratories. He has designed cutting-edge microprocessors at Intel Corporation and won teaching awards at MIT and Stanford.

UC Berkeley Extension
2 Units
10 evenings
Feb. 19 to April 30: Thurs., 6:30-9:30 pm (no meeting on 1 date to be arranged)
Atherton: Florence Moore Bldg, Menlo College, Valparsaiso Ave. near El Camino Real. Enter from Valparaiso between Michaels and Victoria at University Dr. $425 (EDP 323659)

How do I enroll?


Handouts

Syllabus
Lecture Notes 1
Lecture Notes 2
Lecture Notes 3
Lecture Notes 4
Lecture Notes 5
Lecture Notes 7
Lecture Notes 8
Lecture Notes 9
Lecture Notes 10
Problem Set 1
Problem Set 2
Problem Set 3
Problem Set 4
Problem Set 5
Project Description
Project Description Update
SIA Roadmap '97
Fanout-of-4 Inverter Delay
Process Overview
Multiplier Slides

Useful files

PS2 Sample Code
PS2 Solution Script
Class Process File
Sample Iterative Multiplier
Sample Array Multiplier
Ling Adder Model
Buffer-based Repeater Analysis

Online Documentation

HSPICE & MWAVES Manual
Using sue in EE371
EE371 Wire Capacitance Table
Useful Perl links
Sematech Technical Reports
Other VLSI links

Teaching Staff

Instructor: David Harris
Phone: (650) 725-8811
Email: harrisd@alum.mit.edu.

Last modified: Thu Apr 30 15:51:38 PDT 1998