E190AX: Advanced Digital Design

Spring 2022

Instructor: Prof. David Harris
Email: David_Harris@hmc.edu
Office Hours: MonTue 2:35-3:55

Administrative Syllabus Spring 2021	References Digital Design & Computer Architecture RISC-V Spec HMC E190AX Slack Channel Questa Manual Verilator Manual SystemVerilog Standard AHB-Lite Bus Standard	Project Project Requirements riscv-wally Repository ADD Google Drive gates.vsd Visio template
Textbook Reading Responses Preface 1: Intro 2: Tools 3: HDL 4: Wally 5: Privileged 6: Bus 7: Caches 8: Memory Management 9: Branch Prediction 10: Compressed 11: MulDiv 12: Floating Point A: Linux Guide B: GITting Around	Labs Lab 1: Programming Lab 2: Verification Lab 3: Debug Lab 4: Synthesis Lab 5: Design Lab 6: Optimization Final Project: FMA	Lectures 00000: Intro 00001: Tools 00010: Environment 00011: SystemVerilog 00100: Chip Implementation 00101: Single Cycle Processor 00110: Pipelined Processor 00111: Privileged 01000: Bus Interface 01001: Multiply / Divide 01010: Compressed 01011: FMUL 01100: FMA 01101: FDIVSQRT 01110: Project Kickoff 01111: Caches 10000: Memory Management 10001: Branch Prediction 10010: Transcendental Functions 10011: Demos 10100: Demos 10101: Benchmarking 10110: Linux Boot 10111: FPGA Implementation 11000: CMOS Implementation 11001: RISC-V Market 11010: Presentations