From daemon@aw.com Wed Sep 21 21:11:48 1994 Received: from aw.com (aw.com [192.207.117.2]) by leland.Stanford.EDU (8.6.9/8.6.9) with SMTP id VAA13472 for ; Wed, 21 Sep 1994 21:11:45 -0700 Received: by aw.com (5.67b/Spike-2.1) id AA07972; Thu, 22 Sep 1994 00:11:29 -0400 Date: Thu, 22 Sep 1994 00:11:29 -0400 Message-Id: <199409220411.AA07972@aw.com> From: Addison Wesley Publishing Company To: dlheine@leland.stanford.edu Subject: information (complete) ascii Precedence: bulk X-Server: Multihouse Research Mail Server Backend 1.19 X-Info: send mail to ------ begin of information -- ascii -- complete ------ Corrections to Principles of CMOS VLSI DESIGN A Systems Perspective Second Edition by Neil H. E. Weste and Kamran Eshraghian Version 1.0 Compiled by N. Weste with thanks to Professor Fred Rosenberger. this is an unedited text version of the MS Word original. It contains numerous conversion artifacts. For instance, below f(A,B) stands for A/B. One should really use the MS Word original or the RTF version for more accurate equation and text formats. page line correction 16 Fig. 1.9b bottom "01" in F column should be "10" 54 Eq. 2.7 "+ 2fb" should be "- sqrt(2fb)" 63 Fig. 2.12c fourth dot from left should be at the intersection of the two curves marked with 2. 67 7 "VDD - Vtp" should read "VDD + Vtp" 69 5 change ", and hence the switching performance is not affected" to (compare to the inverter responses in Figures 2.19, 2.21, 2.23 and 2.24) 69 24 "a .4 V shift" should read "a .2 V shift" 69 24 change "of the inverter." to "of the inverter (although due to the idealized model, less shift is seen in practice)." 75 4 "should be set to approximately" should read "might be set to approximately" 75 table at bottom of page last column of numbers should be 0.5 1.7 2.2 2.6 3.9 instead of 0.5 2.7 3.2 3.6 3.9 78 18 "in the nonsaturated region" should read "in the nonsaturated or cutoff region" 80 Fig. 2.27 VOL should be VIL and VOH should be VIH 81 2 VOL should be VIL and VOH should be VIH 88 Fig. 2.34 delete small line segment on Idn5 curve 89 11 "nonsaturated" should read "saturated" 89 14 "n nonsaturated" should read "n saturated" 89 15 "n nonsaturated" should read "n saturated" 89 32 "unsaturated" should read "nonsaturated" 186 16 "W = 4 mm" should read "W = 2mm" 186 17 "= 4 * 25.5 * 10-4" should read "= 2 * 25.5 * 10-4" 186 18 " .01" should read ".005" 188 Table 4.4 "2*10-4" should read "3*10-4" (top left entry) 189 25 35 should read 17 189 26 0.014 should read 0.0068 190 4 both 6's should be 3's 190 5 .0052 should read .0028 195 2 change "0.685 -T/1.343s" to "0.685e -T/1.343S" 196 4 change "-t/0.133S" to "-T/0.133S" (uppercase T) 199 20 change "propagation time, tx, over a wire of length x is" to "rise/fall delay, tx, along a wire of length x is" 200 3 change "RCn(n+1)/2" to 0.7*RCn(n+1)/2 200 5 below "n = number of sections" add "(the 0.7 factor accounts for a rise/fall delay to half rail)" 200 8 change "t1 = f(rcl2,2)" to "t1 = 0.7 * f( rcl2,2)" 200 24 change "4" to "2.8" 201 3 change "4"s to 2.8"s 201 4 change "4"s to 2.8"s 201 5 change "8" to "5.6" 201 8 change "16" to "11.2" 201 26 change "6.25" to "0.7 * 6.25" 201 27 change '"25" to "17.5" 201 34 change ".31" to "0.7 * .625" 201 35 change ".31" to ".44" 202 8 change "Eq. (4.28)." to "Eq. (4.28) -( f(rcl2,2))." 202 10 change sentence "The concept of using RC time constants for delay estimation is based on the assumption that the time taken for a signal to reach 63% of its final value approximates the switching point of an inverter." to "The approximations described in this section can (and should) be verified via simulation to check the accuracy of any critical RC delay problem." 202 16 "the area capacitance" should read "the area of the routing capacitance" 205 3 1600 should be 16000 218 Fig. 4.24b labels c and b should be interchanged 220 Fig. 4.27 "nmos-rise" should be "pmos-rise" and "pmos-fall" should be "nmos-fall" at top right of diagram 223 3,4 change "tr=" to "tdr=" and change "tf=" to "tdf=" 223 Table 4.9 delete two lower zeros in first column 227 Eq. 4.60 change all equal (=) to proportional () 227 Eq. 4.61 change all equal (=) to proportional () 228 6 change "equal-sized" to "minimum sized" 228 Eq. 4.62 change all equal (=) to proportional () 230 16 change 2.3-5 to 3-5 233 4 insert "=" after 1.4 mW 235 16 "Vin(t)" should be "Vin(t)" 236 Fig. 4.37(b) t1 t2 and t3 should be subscripted 240 1 add at end "The rise/fall time of the clock is 1ns." 240 12 change "IR = .25 * 25 * 10-3" to "IR = F(CdV,dt) R= F(100*10-12*5,1*10-9) *.25" 240 13 change "= 6.25 mV" to "= 125 mV (also see Section 5.5.16)" 244 Fig 4.40 change "Ids" to "Ids(t) = f(Ids(25),K) K" with last K placed close to vertical axis 247 3 delete "and hold time constraints" and insert "times while the worst power corner would be used to check hold time constraints" 247 5 change "corner" to "corner during simulation or timing verification" 248 Table 4.11 under TESTS column, first line change to "Power dissipation (DC), clock races, hold time constraints" second line change to "Circuit speed, setup time constraints" 249 Eq. 4.82 delete "100%" at end of equation 249 22 Insert after "area of the chip is increased." The latter two models account for the clustering of defects (i.e. they are not independent)." 251 36 change "l/a" to 1/a" 253 24 change "l/a" to 1/a" 253 26 change "l/a2" to 1/a2" 253 26 change "l/a3"to 1/a3" 255 8 insert after "wiring capacitances." In addition, the resistance of wires increases and becomes more important relative to transistor resistance." 256 Prob. 2 change "The testing cost for each is $1.50" to "The testing cost for each die (prior to packaging) is $1.50" 256 Prob 3 change "Ln=Lp=1m" to "Ln=Lp=1m, Cg = .0017 pF/m2, assume source, drain and other stray capacitance is equal to gate capacitance of stage) 257 Prob 7 add at end "(Ignore inductive effects)" 265 11 change "tr the worst-case rise" to "tdr the worst-case rise delay" 265 12-13 change "(ignoring parasitic capacitances in transistors)" to "(ignoring body effect - see Section 4.5.4.5)" 265 14 and 25 change "tr" to "tdr" 266 16 change "tr" to "tdr" 266 22 change "the fall time, tf" to "the fall delay time, tdf" 266 23 change "tf" to "tdf" 267 9 change "tr = tf" to "tdr = tdf" 267 13 change "Wp=F(Wn,m)" to "bpWp=F(bnWn,m)" 267 14 change "1/mth" to "bn/mbpth" 267 18 change "tr" to "tdr" 267 19 change "tf" to "tdf" 267 21 change "6" to "6.4" and "12.3" to "12.8" 267 22 change "Tinput-rise/fall" to "tinput-rise/fall" 267 28 change "(the transistors" to "(the n-transistors" 268 1 change "rCg (= Cd) = .005pF" to "rCg (= Cd) = .005pF (Cg = .003pF, r=1.7); Wp = 2Wn" 268 2 change "tf-nand" to "tdf-nand" 269 2 change "tf-nand" to "tdf-nand" 287 Fig. 5.16(b) poly gates have to be connected by metal 298 11 VDD should read VSS 308 Fig. 5.36(a) spurious line in n-pull down tree 333 10 change "Section 5.6.3" to "Section 5.6.4" 371 5 change last Ln in line to Lp 531 Fig. 8.19b change G<2> to -G<2> change -P<3> to -T3 change G<3> to -G<3> change P<3> to T3 change -T2 to -T3 change T2 to T3 325 Fig. 5.51 reversed TG 525 Fig. 8.12 misplaced wire on TG adder 708 change "metallurical" to metallurgical" and add after "metal migration, 238-239, 361" ------ end of information -- ascii -- complete ------